留学生代考 PIC18,” , , 2008.

UART Reception: Error Tolerance
• Frequency drift of ±0.5 bit can be tolerated in the space of 10 bits (8 bits + start/stop bits).
• Receiver and transmitter local sample clocks must be within ±5%.
• e.g., % Error = (9615 – 9600)/9600 = 0.16% < 5% PIC18 UART Reception • USART peripheral needs to be enabled (RCSTA.SPEN) • Receiving on UART needs to be enabled (RCSTA.CREN) • The PIR1.RCIF flag will be raised by the microcontroller after it received a valid byte. • The user needs to copy the received byte out of RCREG. This will automatically reset RCIF. PIC18 UART Reception This example receives bytes and output to PORTD clrf TRISD movlw b'00100100' movwf TXSTA movlw b'10010000' movwf RCSTA movlw 25 movwf SPBRG ; set PORTD as output ; TXEN = 1, SYNC = 0, BRGH = 1 ; SPEN = 1, CREN = 1 ; Set Baud rate for 9600 ; wait until receiving a complete byte ; move the received byte to PORTD MainLoop: btfss PIR1, RCIF bra MainLoop movff RCREG, PORTD bra MainLoop Reception Overflow Error (OERR) 2-deep RCREG pipeline What is Overflow Error? • Normally, once a complete byte is received, it would be read from RCREG to another register. • If a third byte arrives before the previous two bytes are read→no room to store the third byte→Overflow Error occurs Overflow Error: A Detailed Look Overflow Error: A Detailed Look 1. Received Word 1, which occupies the lower RCREG buffer. RCIF is set. 2. Received Word 2, which occupies the upper RCREG buffer. 3. 3rd byte arrives. RCREG is full. OERR is set. 3rd byte is lost. 4. Word 1 is read. Word 2 moves to the lower RCREG buffer. RCIF remains set. 5. Word 2 is read. RCIF is cleared. 6. OERR must be reset by clearing CREN and then setting it again. No further bytes will be received until OERR is cleared. You should be able to .... 1. Explain why voltage conversion using MAX232 is needed. 2. Explain the operation of the PIC18 UART module. 3. Explain overflow and framing errors in UART reception. 4. Program the UART module to perform data transmission and reception. 7.2: Inter-integrated Circuit Interface (I2C) Inter-Integrated Circuit (I2C) • Synchronous serial interface protocol for transmitting and receiving data from external devices. • I2C uses two lines: Serial CLock Signal (SCL) and Serial DAta (SDA) • Data flow in I2C is bidirectional (half duplex). Master(s) and Slave(s) • Master is responsible for: – Initializing/stopping data transfer – Control data transfer direction – Generating clock signals • Typically, the microcontroller operates as the master and peripheral components (e.g., memory) as a slave. Hardware Configuration • SDA and SCL lines have two possible states: float high and driven low. • Both the SDA and SCL lines are pulled up to VDD by pull-up resistors at Idle state • When the switch of the master or slave turns on, the signal is pulled down because there is current flowing from the I2C bus to the switch. Start and Stop Conditions • I2C bus allows for more than one device to take over as master (although not simultaneously). • Before a microcontroller transfers data to a slave, it needs to send a START condition. • When transfer of data ends, the microcontroller needs to relinquish the control by sending a STOP condition. Data Transfer between Master and Slave 1. Master sends out START condition 2. Master sends out a Control Byte, consisting of the 7-bit slave address and a bit (the last bit) indicating whether the master reads from or writes to the slave. 3. Data bytes are sent until a STOP condition is asserted by the master. Control Byte PIC18 MSSP Module in I2C Mode • Registers supporting I2C operations: – MSSP Control Register 1 (SSPCON1) – MSSP Control Register 2 (SSPCON2) – MSSP Status Register (SSPSTAT) – Serial Receive/Transmit Buffer (SSPBUF) – MSSP Shift Register (SSPSR)—not directly accessible – MSSP Address Register (SSPADD) Baud Rate Generator (BRG) • Time required to shift out one bit of data = 2TBRG, where TBRG = time required for the BRG counter to count down to 0 from an initial value • The initial value of BRG counter is placed in the lower 7 bit of register SSPADD (i.e., SSPADD<0:6>), which is set by users.
• BRG counter is decremented twice per instruction cycle.

Baud Rate Generator (BRG)
e.g., If SSPADD = 03, Clock freq. = FOSC = 4MHz, what is the baud rate?

TBRG = (4 TOSC /2) x (SSPADD<0:6>+1) Baud Rate = 1/(2 TBRG)
= FOSC / [4  (SSPADD<0:6>+1)] where TOSC = Oscillation period of clock FOSC = 1/TOSC = Clock frequency

Baud Rate Example
• What is the initial value we need to load to the SSPADD register if we want to set the baud rate to be 100kHz? Assume the clock has a frequency of 4MHz.
• Let x = initial value
• Baud Rate = 4MHz / [4  (x+1)] = 100kHz
• x = 0x09

Start Condition
• Start condition is initiated by writing to SEN bit (SSPCONS2<0>)
• S bit (SSPSTAT<3>) is set during start
• When completed, SEN bit is cleared and SSPIF is set.
Figure 11.2 I2C Start condition

Assert a Start Condition
• Assert the start condition by setting the SEN bit in SSPCON2:
bsf SSPCON2, SEN
• Wait for the start condition to complete
I2C_WaitFinish: bcf PIR1, SSPIF I2C_WaitLoop: btfss PIR1, SSPIF
bra I2C_WaitLoop

Stop Condition

Stop Condition
• Assert the stop condition by setting the PEN bit (SSPCON2<2>):
bsf SSPCON2, PEN
• Wait for SSPIF to get asserted, indicating completion:
bra I2C_WaitFinish

Repeated Start Condition
Imagine this situation:
• Master device wants to change data transfer direction (i.e., write to read or vice versa) but without losing control of the line
• Need to send out a new control byte (Last bit of the control byte determines data transfer direction.)
• But, control byte needs to be preceded by a Start condition.
Figure 11.2 I2C Start condition
• Start condition can only be asserted if both SDA and SCL float high→usually achieved SDA by asserting a Stop condition.
• Master cannot assert a Stop condition because it does not want to lose control of the line.
• Master asserts a Repeated Start condition Control Byte
Figure 11.3 Stop (P) condition

Repeated Start Condition
• So, is it possible to bring SDA and SCL high, but without asserting a Stop condition?
• Solution: Bring SDA high first, then bring SCL high.
Figure 11.3 Stop (P) condition

Repeated Start Condition Timing
• Activate RSEN bit (SSPCON2<1>)
• S bit (SSPSTAT<3>) is set during repeated start
• When completed, RSEN bit is cleared and
SSPIF is set.
Let both SDA and SCL to float high without asserting a STOP condition

Assert a Repeated Start Condition
• Assert the repeated start condition by setting the RSEN bit in SSPCON2:
bsf SSPCON2, RSEN
• Wait for SSPIF to get asserted:
bra I2C_WaitFinish

Transmission
• Transmission of a data byte or an address is achieved by writing to the SSPBUF register. BF flag (SSPSTAT<0>) is set.
• Data is clocked into the receiver on SCL rising edge.
• Changes on SDA must only occur when SCL is low.

Transmission
• To write data/address to I2C bus:
– First write to WREG register
– Then move the value of WREG to SSPBUF
movwf SSPBUF
– Finally, wait for the SSPIF signal to get asserted:
bra I2C_WaitFinish

• To start reception:
bsf SSPCON2, RCEN
• Wait for SSPIF to get asserted:
bra I2C_WaitFinish
• Write SSPBUF into a register for further processing:
movff SSPBUF, I2C_BYTE

Acknowledge Reception
• Clear the ACKDT bit (SSPCON2<5>) to acknowledge reception. Set ACKDT to send a negative acknowledge
• Set ACKEN to activate the acknowledgement process

Acknowledge Reception
• Set/ClearACKDT:
bsf (bcf) SSPCON2, ACKDT
• Set ACKEN to activate acknowledgement:
bsf SSPCON2, ACKEN
• Wait for SSPIF to get asserted, indicating completion:
bra I2C_WaitFinish

I2C Interface with AT24C02 EEPROM
• AT24C02 provides 2048 bits of serial EEPROM organized as 256 8-bit words.
• Control byte
• A2, A1 and A0 are determined by inputs to the corresponding pins
• R = 0 for write operation and R = 1 for read operation

Byte Write
1. The master asserts the Start condition
2. The master sends the control byte to AT24C02
3. AT24C02 acknowledges the reception of the control byte
4. The master sends the word address (address of the word inside AT24C02 ranges from 00 to FF) to AT24C02
5. AT24C02 acknowledges the reception of the word address
6. The master sends the data byte to AT24C02 7. The master asserts the Stop condition

Byte Write
Recap what we defined
Write to EEPROM

Acknowledgement Polling
• Once the Stop condition has been issued after the write operation, the EEPROM enters the internal write cycle.
• The duration of this cycle depends on the device.
• Acknowledgement polling involves sending a start condition followed by the control byte.
• If the internal write cycle has not been completed, the EEPROM would response with a NAK; otherwise it would response with an ACK.

Page Write
• Instead of sending a Stop condition after the transmission of the 1st byte, send 7 more bytes.
• If more than 8 bytes are written, the data word address would “roll over”.

1. Perform Steps 1 to 5 of Byte Write to define the device address and word address to read from.
2. The master asserts the Repeated Start condition
3. The master sends the control byte with last bit equal to 1 indicating a read operation
4. AT24C02 acknowledges the reception of the control byte
5. The master asserts the receive condition
6. The master receives the data byte and asserts NACK to the EEPROM
7. The master asserts the stop condition

Conditions previously defined
Byte Read from EEPROM

Sequential Read
• Instead of sending a NACK after the first byte is read, the master sends out an ACK.
• The operation terminates when the master sends out a NACK bit and assert the stop condition
• Sequential read is not limited to 8 bytes.

You should be able to …
• Understand the characteristics of the I2C protocol
• Describe different conditions that needs to be asserted during a I2C transfer.
• Design the baud rate of the data transfer by setting the values in SSPADD.
• Describe and implement different methods of interfacing with the AT24C02 EEPROM.

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