Von Neumann and MIPS
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Notations
■ Sets of Bits
◆ A[3:0]denotesasetof4bits:A ,A ,A ,A
3210
◆ The content of an n-bit register Rx is referred to as Rx[n-1:0]
★ RXn-1 is the most significant bit (MSB), or leftmost bit
★ RX0 is the least significant bit (LSB), or rightmost bit
★ Given RX[31:0], RX[7:4] refers to the four bits from RX7 down to RX4
■ Bit Assignment
◆ R2[5:0] ⇐ R1[13:8]
★ Means that bits 5 to 0 of register R2 get assigned the values of bits 13 to 8 of register R1. ■ Contents
★ (Reg1) means “content of Reg1”
★ Mem[loc] means “content of memory location loc” (i.e., loc is the address)
★ [Reg1] means the “contents of memory at address in Reg1”
MIPS Memory
■ 32-bit “flat” memory model
◆ Address 0x00000000 to 0xFFFFFFFF ◆ How much memory is that?
“Endian”-ness of Memory addressing
■ MIPS is byte-addressable
■ Little Endian byte ordering
◆ Compare to Big Endian… (e.g. AVR or ARM)
Origin of the word “Endian”
• One of the earliest literary instances of “satire”
• conflict between 2 groups of Lilliputians divided into those breaking the shell of a boiled egg from the big end or from the little end. Gulliver called them the “Big-Endians” and the “Little-Endians”
break the shell of a boiled egg from the little end!
break the shell of a boiled egg from the big end!
Little Endians
Big Endians
Endianness
Big Endian: Most significant byte occupying lower address position Little Endian: Least significant byte occupying lower address position
Endianness: Memory aid for exams
Lol
Least significant byte of data occupies lower address position in memory!
Most significant byte of data occupies lower address position in memory!
Little Endians
Big Endians
Class Poll
Given the following byte addressable word aligned main memory:
1. Assume Big Endian ordering,
Then what is the word stored at mem[44]?
2. Assume Little Endian ordering,
Then what is the word stored at mem[44]?
Least significant byte of data occupies lower address position in memory!
Most significant byte of data occupies lower address position in memory!
Little Endians
Big Endians
MIPS Registers(explored again later..)
Register File
■ Temporary can be used $t0…$t9 ◆ Procedures can destroy these
■ Saved can be used $s0..$s7, but are caller save ◆ Procedures must save/restore these
■ $zero (or $0) is always 0
■ $a0..a3 Are passed to functions as parameters
■ $v0..v1 Are returned from functions
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Memory “Segments”
■ Three segments for now
◆ Reserved:
★ 0x0000_0000to0x0040_0000 ★ SpecialcodeforI/OandOS
◆ ProgramText:
★ 0x0040_0000to0x1000_0000
★ Machinecodeforyourinstructions!
◆ StaticData
★ 0x1001_0000to0x1004_0000
★ Data that is allocated before your program runs
MIPS Example
Not Divisible By Four Program
Sequence of 5 Instructions
■
Memory Unit
■ Instructions stored in memory.
■ The first instruction is always at 0x0040 0000
■ Each instruction is 32 bits long (4 Bytes, 1 byte = 8 bits)
■ 5 instructions = 5 * 4 bytes = 20 bytes (size of the program).
■ Instructions stored sequentially in memory with the address
of the next instruction being +4 of the previous instruction
MIPS Instructions
• All instructions exactly 32 bits wide
• Different formats for different purposes
• Similarities in formats ease implementation
6 bits 5 bits
5 bits 5 bits
5 bits
5 bits 16 bits
6 bits
R-Format 0
I-Format
J-Format 31 0
op
rs
rt
rd
shamt
funct
31
6 bits
5 bits
op
rs
rt
offset
31 0
6 bits 26 bits
op
address
MIPS Instruction Basics
R-type instructions: ■ , $t2, $t4
■ op rs, rt, rd, shift amount, funct:
★ rd – destination, rs – source 1, rt source 2
or
$v0
op – 6 bits
rs – 5 bits
rt – 5 bits
rd – 5 bits
shamt – 5 bits
funct – 6 bits
■ or$v0,$t2,$t4