Abstraction & Digital Logic: From Transistors to Gates
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NOT gate (Inverter )
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Vdd V (Logic 1) 0 V (Logic 0)
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The Inverter / NOT gate
• • • •
Single Input, Single Output Logic gate
Most basic Logic Gate
If input is logic High( 1), output is logic Low(0) If input is logic Low(0), output is logic High(1)
input
output
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Truth Table (abbrvtd to T.T.)
• • •
A truth table helps give tabular representation of the behavior of a logic gate A truth table with have columns for the inputs and for the output
Truth table of an inverter/ NOT gate:
Input
1
0
Output
0
1
input
output
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Logic Gates with >1 input signal
• •
Let us introduce the AND gate:
An AND gate can have any number of input signals
An AND gate will output a Logic High (1) ONLY when ALL of the inputs are at logic High(1)
Else output is logic Low(0)
• •
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AND gate Truth Table
in1
Goes through all 4 possible values for in1,in2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
in2
0
1
0
1
0
1
0
1
out
Goes through all 8 possible values for in1,in2
0
0
0
0
0
0
0
1
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0
1
1
in1
0
in2
0
1
0
1
in3
0
0
0
1
out
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Truth Table for n inputs
• If a Logic Gate has n number of inputs, then its truth table will have 2n number of rows.
• Corresponding to each such distinct pattern of inputs in a row, we will have a corresponding output value (1 or 0)
• Thus, if the AND gate had 4 inputs, it would have had 24 = 16 rows in its truth table
• Thus, if the AND gate had 17 inputs, it would have had 217 = 131072 rows in its truth
table!
• When drawing a truth table for an n input logic gate, make sure each row has a unique pattern of 1s and 0s!
• Example, in a 4 input logic gate truth table, the input pattern 1011 must appear only once in your truth table!
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The OR logic gate
• •
Let us introduce the OR gate:
An OR gate can have any number of input signals
An OR gate will output 0 ONLY when ALL of the inputs are 0 Else output is 1
• •
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OR gate Truth Table
in1
Goes through all 4 possible values for in1,in2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
in2
0
1
0
1
0
1
0
1
out
0
1
Goes through all 8 possible values for in1,in2
1
1
1
1
1
1
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0
1
1
in1
0
in2
0
1
0
1
in3
0
1
1
1
out
10
1
1
NAND logic gate
• In a NAND logic gate, the NOT gate!
in1
0
0
in2
0
1
0
1
out
1
1
1
0
output of an AND gate is simply connected to the input of a
Truth Table of 3 input NAND gate
in1
0
0
0
0
1
1
1
1
in2
0
0
1
1
0
0
1
1
in3
0
1
0
1
0
1
0
1
11
out
1
1
1
1
Truth Table of 2 input NAND gate
1
1
1
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1
1
NOR logic gate
• In a NOR logic gate, the o NOT gate!
in1
0
0
in2
0
1
0
1
out
1
0
0
0
utput of an OR gate is simply connected to the input of a
Truth Table of 3 input NOR gate
in1
0
0
0
0
1
1
1
1
in2
0
0
1
1
0
0
1
1
in3
0
1
0
1
0
1
0
1
12
out
1
0
0
0
Truth Table of 2 input NOR gate
0
0
0
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Let us return back to CMOS!
• Up till now, we considered the AND/OR gates at a higher abstraction level
• We essentially treated them as black boxes.
• Let us see under the hood and find out how CMOS technology actually enables us to physically create the logic gates!
• Recall the behaviour of pMOS and nMOS transistors:
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1 1
0 NAND gate
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0 0 0
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A general CM
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OS circuit
Pull Up Network (PUN)
Q. How to determine Out without solving for entire truth table???
A. Follow Output path through either the PUN (towards Vdd) or the PDN (towards gnd)
PDN approach: Under what conditions does Out have a direct path to gnd??
Out = 0, (when AAND B ON) OR (whenCANDDON)
Pull Down Network (PDN)
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