Von Neumann and MIPS
Memory “Segments”
■ Three segments for now
◆ Reserved:
★ 0x0000_0000to0x0040_0000 ★ SpecialcodeforI/OandOS
◆ ProgramText:
★ 0x0040_0000to0x1000_0000
★ Machinecodeforyourinstructions!
◆ StaticData
★ 0x1001_0000to0x1004_0000
★ Data that is allocated before your program runs
MIPS Example
Not Divisible By Four Program
Sequence of 5 Instructions
■
Memory Unit
■ Instructions stored in memory.
■ The first instruction is always at 0x0040 0000
■ Each instruction is 32 bits long (4 Bytes, 1 byte = 8 bits)
■ 5 instructions = 5 * 4 bytes = 20 bytes (size of the program).
■ Instructions stored sequentially in memory with the address
of the next instruction being +4 of the previous instruction
MIPS Instructions
• All instructions exactly 32 bits wide
• Different formats for different purposes
• Similarities in formats ease implementation
6 bits 5 bits
5 bits 5 bits
5 bits
5 bits 16 bits
6 bits
R-Format 0
I-Format
J-Format 31 0
op
rs
rt
rd
shamt
funct
31
6 bits
5 bits
op
rs
rt
offset
31 0
6 bits 26 bits
op
address
MIPS Instruction Basics
R-type instructions: ■ , $t2, $t4
■ op rs, rt, rd, shift amount, funct:
★ rd – destination, rs – source 1, rt source 2
This instruction is an example of Register Addressing
or
$v0
op – 6 bits
rs – 5 bits
rt – 5 bits
rd – 5 bits
shamt – 5 bits
funct – 6 bits
■ or$v0,$t2,$t4
I-Type Instructions
■
◆ Example (using decimal notation): ★ ADDI $t1, $t2, 23
★ $t1 = $t2 + 23
Arithmetic Immediate
◆ Can use hex notation (useful for masking): ★ ANDI $t1, $t2, 0x000F
★ $t1 = $t2 & 0x000F
This instruction is an example of Immediate Addressing
Logical Operations
Regarding SUB instructions
★ SUB $t1, $t2, $t3
– Means ($t1) = ($t2) – ($t3)
MIPS Overview – Commands
MIPS instructions can be broken down into 3 categories:
■ Data Movement
◆ Move data between memory and registers ★ For example: lw is load word, sw is store word
■ Operate
◆ Manipulate data directly
★ For example: add is addition, xor is logical ■ Control
◆ Change the sequence of instruction execution
★ For example: b is branch, jal is jump and link, ret is return
Data-Movement: Load Instructions
■ Move data from memory to a register Data transfer
Register
Memory
12
Endianness: Memory aid for exams
Lol
Least significant byte of data occupies lower address position in memory!
Most significant byte of data occupies lower address position in memory!
Little Endians
Big Endians
Base addressing
■ lw $t1, ($t2)
◆ $t2 contains a 32-bit address ◆ Effective address is $t2
◆ ($t1) = memory[$t2]
■ NOTE: lw $t1, $t2 is not valid syntax! Example:
Assume four 32-bit registers, Little Endian ordering in memory Reg0
Memory address
0x10
0xA0
0x09 10
0x00 11
0x99
0xA5
0x54 14 0xFD 15 0x29 16 0xA5 17 0x01 18 0xFF 19
1210
Reg1 Reg2
Reg3
lw Reg1, (Reg2);
(Reg1)=?
(Reg1)= 0x FD 54 A5 99
8
9
12
13
Base + offset addressing
■ lw $t1, 4($t2)
◆ $t2 contains a 32-bit address
◆ Instruction contains 16-bit immediate offset (4) ◆ Effectiveaddressis$t2+4
◆ $t1=memory[$t2+4]
■ NOTE: lw $t1, 0($t2) is the same as indirect addressing!
■ Immediate offset is 16-bit *signed* and we can load adjacent
words:
◆ lw$t1,-4($t2) ◆ lw$t2,0($t2) ◆ lw$t3,4($t2)
Base addressing
Example:
Assume four 32-bit registers, Little Endian ordering in memory, byte addressable (always implicit if not mentioned)
Reg0
Reg1 Reg2
Reg3
Memory
address
8
9 10
11
12
13 14
15 16
17 18
19
0x10
0xA0
0x09
0x00
0x99
0xA5
0x54
0xFD
0x29
0xA5
0x01
0xFF
1210
Problem 1:
lw Reg1, 0(Reg2);
(Reg1)=?
(Reg1)= 0x FD 54 A5 99
Problem 2:
lw Reg1, 4(Reg2);
(Reg1)=?
(Reg1)= 0x FF 01 A5 29
Problem 3:
lw Reg1, -4(Reg2);
(Reg1)=?
(Reg1)= 0x 00 09 A0 10
Load data sizes
■ Words are 32-bit values
◆ Load word (lw)
◆ Samesizeastheregisters ◆ Samesizeastheaddresses
■ Half-Words
◆ Load half word (lh)
◆ Are 16-bit values
◆ Samesizeastheimmediatevalues
■ Bytes
◆ Load byte (lb) ◆ Are 8-bit values
Data sizes (cont’d)
■ Where are half word and bytes placed? ◆ Half word is put in lower register bits [15:0] ◆ Byte is put in lower register byte [7:0]
■ What about the other bits?
◆ Half word
★ LH fills upper bits [31:16] with sign ★ LHU fillers upper bits [31:16] with 0
◆ Byte
★ LB fills upper bits [31:8] with sign ★ LBU fillers upper bits [31:8] with 0
Data-Movement: Store Instructions ■ Move data from memory to a register
19
Register
Data transfer
Memory
Data-Movement: Stores
■ Stores are similar to loads…
◆ Address modes are the same.
◆ Data sizes are the same.
★ Upper bits are ignored for byte and half word writes
◆ Except… register contents are put in memory. ★ sw $t1, 4($t2)
★ Memory[$t2+4] = ($t1)
Base addressing
■ sw $t1, ($t2)
◆ $t2 contains a 32-bit address ◆ Effective address is $t2
◆ memory[$t2] = ($t1)
■ NOTE: sw $t1, $t2 is not valid syntax! Example:
Memory address 8
9 10
11
12
BA 13
FE 14
CA 15 16
17 18
19
Assume four 32-bit registers, Little Endian ordering in memory Reg0
0xCAFEBABE Reg1
sw Reg1, (Reg2); Mem[Reg2]=?
Mem[Reg2]= 0x CA FE BA BE
1210
Reg2 Reg3
BE
Summary of Loads/Stores
Use the GREEN!
Don’t use Grey!