Digital Design
Synchronous and Asynchronous Finite State Machine Implementation Pre-Assignment Preparation
Why? So that students can implement a sophisticated synchronous and asynchronous finite state machines on a programmable logic device. In addition, students will teach themselves yet another language, this time a hardware definition language called Verilog. Finally, it will become apparent that the simplistic methods of logic minimisation are incapable of dealing with even relatively simple real-world specifications.
1.0 Overview
This is an assignment tasked with encouraging you to teach yourself something new.
The early stages of the Digital Design module introduced synchronous finite state machines and showed you how to design these in the simplest, most-reliable and formally correct manner. The end result was a small number of sum-of-products transition equations that could be directly implemented using logic gates or as optimised sub-routines for hardware description languages.
When programmable logic devices were first introduced, languages such as CUPL and ABEL permitted one-to-one control of the logic gates. As the hardware complexity increased, such languages were abandoned and schematic capture of circuit diagrams was used in the early stages of many undergraduate courses in order to implement digital circuits. Currently, even schematic circuit diagrams have been abandoned by the software vendors. This leaves two serious possibilities of implementing circuits on large gate arrays; using VHDL or using Verilog.
For the purposes of this assignment you will use Verilog. This has been chosen because it has a simpler structure with many similarities to the C language of which you are familiar. The choice gives you something else to add to your CV. You will also undertake a comprehensive VHDL component as part of this module.
Finally, when you trawl the internet in search of ways to fix error messages you will find many posts saying ‘don’t even attempt to implement asynchronous machines on large gate arrays’. Although this is sound advice for the structure of modern FPGAs, you will find that appropriate design techniques prevail.
Some sections of this guidance sheet have been reproduced verbatim from Dr Quigley’s notes. So here goes with my attempt at guiding you through the assignment …….
2.0 The Field note Book
Start on a new page with a title date and introduction. The introduction should contain a black-box style diagram of your synchronous finite state machine and later your electronic lock. Place inputs on the left of the diagram and outputs on the right. I would suggest that you turn-over the page and start a hardware, Vivado and Verilog tutorial section.
3.0 Nexys 4 DDR Hardware
Under normal circumstances (pre-Covid19), you would have been supplied with a Nexys 4 DDR hardware development board, see Figure 1. The important items to note are: sixteen input switches
(8), sixteen LEDs (7), five push-buttons (11) USB power and programming port (2) and on-off switch (23).
Figure 1: Nexys 4 DDR Board (https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-4- ddr/nexys4ddr_rm.pdf)
The board supports a 450 MHz Artix-7 FPGA. This contains 15,850 slices (each slice contains four 6-input LUTs and 8 flip-flops), 4860 Kbits of fast block RAM and 240 DSP slices. I would not expect you to use more than 1% of the resources for this assignment.
The design and implementation process is almost completely implemented in software, only at the last possible moment is the hardware configured. This means that for larger designs, it is possible to work on the system (using simulation if necessary) and get many of the bugs out of the design before taking the time to implement it. The actual process of configuring the hardware consists of generating a programming file, which is then streamed onto the chip via a connection to the USB port on the PC.
3.1 The Design Process
The process of getting an idea into a hardware implementation requires a series of procedures to be followed:
• First, the components of the design must be planned and written using a language such as
Verilog.
• Second, the Verilog designs must be synthesised. This procedure converts the Verilog into a series of logical components which can then be constructed in the hardware. Not all Verilog code can be synthesised and it is common for a particular design to be “impossible”. Often you have to rewrite portions of Verilog code in such a way that synthesis becomes possible. As you become more experienced in writing Verilog, you will tend to write better quality, more synthesisable code.
• The third stage is the implementation process. This consists of a number of sub-processes. This part of the procedure is responsible for planning the positioning of the logical components on the actual chip, as well as connecting them both together, and to any external components that are required.
• The final stage consists of configuring the chip (hardware) according to the design that the software has developed. This is done by generating a coded file which is then streamed to the starter board using designated programming software.
File storage considerations. On the networked computers in the labs, you can store your working files on the local hard disk but these files will be deleted after you log out. Alternatively, you can store your working files on your network drive, but the performance of the design software may be unacceptable at times of high network load.
It is suggested that you store your design files on the local hard drive whilst you are working on them, but you must make sure that you copy these files onto your network drive before you log out. Often, you will have to start a new project each time you log onto a Departmental machine and import the source, constraint and board files.
3.2 Vivado
You will be using the Xilinx Vivado software suite. There is a free version available for download and it is suggested that make good use of this to familiarise yourself with the material prior to entering the laboratory.
Action 1: Download the latest Xilinx Design Suite HLx Editions (e.g. 2019.2 at https://www.xilinx.com/support/download.html). You will be required to register your details and generate an account.
Open the latest version of Vivado (from the Xilinx Design Tools section of the start menu). This is the main interface for the Xilinx integrated development environment (IDE) which you will be using during this assignment. The IDE is capable of managing a complete project from its first design entry, through the synthesis and implementation processes right up to the programming of the chip. The first time you use it, the software will take several minutes to load (and you may get a time-out message which you can safely ignore). This is due to an interaction between the software and the virus scanner. Subsequent start-ups during the same login session should be much faster. Eventually you will get to the quick start screen (your screen will initially have a blank ‘recent projects’ pane):
Click on “Create Project” (top-left of Quick Start), then click on “Next”. Set the designs location to the place where you will store your files. If you choose the network drive, the software may believe that it does not have write access to the root of the network, so you may have to create the designs directory manually using File Explorer. Enter the project title “MSc_Digital_Design_Freagment_1” – Note that the final project directory will alter to match the project title.
Don’t worry if the software changes backslashes \ in your file names (which are standard for Microsoft Windows) into forward slashes / (which are standard in Unix-like environments). It won’t make any difference to how the software works.
In the “Project Type” options choose “RTL Project” and clear “Do not specify sources at this time”. Then click Next.
You will now be asked to add sources. Select “Verilog” in the pull-down menu on the bottom-left.
Click on “Create File” (middle-right). A new pop-up will open. Add a name for the first of the source files to be added to the project such as “MSc_Source_1” and click OK. You will see that a new source file has been added to the list within the “Add Sources” pane. Click Next.
You will now be asked to add a constraints file. Open your Canvas page and locate the ‘Nexys-4- DDR-MSc_Fragment_1.xdc’ file and download it to your working directory. Select “Add Files” (middle-right) and select the ‘Nexys-4-DDR-MSc_Fragment_1.xdc” file. Click Next.
A “Default Part” panel will appear. You will notice a carefully concealed ‘Parts’ | ‘Boards’ tabs (top-left). Click on the “Boards” tab, then scroll down the list of boards until you find the Nexys 4 DDR. Click on this row so that it is highlighted:
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3.2.1 What to do if no Nexys 4 DDR board file is visible
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The Vivado software uses UML descriptions of hardware development boards under a directory called ‘Board File’. A new installation, or an automatic update of the software, may require the board files to be replaced. This may require creative work-rounds of the required administrative privileges.
If you are installing on your own laptop, the steps are as follows:
If you are patching a University PC, the steps are as follows:
Visit the Digilent site and download the zip file containing the boards (https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1). I have also added this zip file to Canvas in the Finite State Machines Assignment section.
Extract the contents of this file and place the extracted files into the Vivado directory C:\Xilinx\Vivado\20xx.x\data\boards\board_files (if you have administrative control).
Restart Vivado
Visit the Digilent site and download the zip file containing the boards (https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1). I have also added this zip file to Canvas in the Finite State Machines Assignment section.
Extract the contents of this file and place the extracted files into your network drive (or somewhere convenient).
Navigate through the extracted files to find the Nexys 4 DDR directory.
Copy the Nexys 4 DDR directory and contents to your source location.
Scroll down to the bottom of the Quick Start screen to the ‘Tcl Console’. At the very
bottom there is a long-thin rectangular box that allows you to type in console commands. Type in: ‘set_param board.repoPaths C:/cdimage/pra000/Nexys 4 DDR/’ (changing
the path names to suit).
You should now be able to ‘Create Project’ and select boards in the expected manner.
In the New Project pop-up window click “Next”. You will be given a summary window of the project that is about to be created. Check that the board and FPGA settings are correct (the board should be Nexys 4 DDR and the FPGA should be XC7A100TCSG324-1. If there is a mistake, then click “Back” and fix it. If everything is OK then click “Finish”. The project will be initialized and you will then see the main window of the Vivado IDE and a “Define Module” pop-up. Enter four input Port Names (sw_A, sw_B, sw_C, sw_D) and six output port names (led_A, led_B, led_C, led_D, led_E, led_F). click “OK” in the “Define Module” pop-up. Click “OK”.
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The key parts of the IDE are:
1. The Design Flow Navigator
This contains a list of the various operations that you can perform on your design (e.g. Synthesis, Implementation, etc.). Generally, if a green triangle appears, then the system is waiting for you to run this stage. If the green triangle turns to a grey triangle, the results are up-to-date.
2. The Sources window
This contains a list of the files that you are working on.
3. The Properties window
This contains a list of the properties of the files that you are working on.
4. The Workspace Area
When you are editing your design files they will appear here.
5. The Status Bar
At the beginning of your design this won’t say anything interesting (it will probably just say “Ready”). As you create your design, the status bar will tell you what the tools are currently working on. Some designs can take a long time to synthesize, and if you ever find yourself wondering what the tools are doing and whether they have finished yet, then have a look at the status bar. When the tools are working on something there will be a rotating green progress circle in the status bar and the name of the operation in progress.
6. The Results Windows Area
There is a series of tabbed windows here that give information about errors, warnings, timing reports and so on. You will often have to select through all the tabs as they provide different information about errors that you are bound to encounter.
4.0 Verilog
Verilog is a hardware description language with a syntax similar to the C language. Many online tutorials exist, but the one most frequently visited is http://www.asic-world.com/verilog/veritut.html. A rainy Sunday working through this in conjunction with Vivado and the Nexys 4 DDR board should ensure that you are reasonably competent with the language.
As usual, we will start with a black-box approach, although this time we will call it a module. We will place inputs on the left and outputs on the right. Let us start with a very simple example shown in Figure 2. We will take the rightmost switch on the Nexys 4 DDR board and connect it via a buffer to the rightmost LED. We will also invert the switch signal and route it to an adjacent LED.
sw_A sw_B sw_C sw_D
Inputs
led_A led_B
led_C led_D led_E
led_F Outputs
Black Box or Verilog Module
Figure 2: Verilog module to be implemented in hardware
In the “Sources” panel you will see a “Design Sources” heading and under that the name of your source file e.g. “MSc_Source_1”. Double click on this source file to allow editing within the workspace panel. You will note that Vivado has partially populated the comments (delimited by ‘//’ symbols) and the module. Vivado also populates the parameters of the module with input and output keywords such as:
module MSc_Source_1(
input sw_A,
input sw_B,
input sw_C,
input sw_D,
output led_A,
output led_B,
output led_C,
output led_D,
output led_E,
output led_F
);
endmodule
Many programmers would add the input/output port declarations within the module, e.g.:
module DD_Source_1(sw_A,sw_B,sw_C,sw_D,led_A,led_B,led_C,led_D,led_E,led_F); input sw_A;
input sw_B;
input sw_C;
input sw_D;
output led_A;
output led_B;
output led_C;
output led_D;
output led_E;
output led_F;
endmodule
Note that all commands are semicolon delimited.
If we want to add some combinatorial logic to implement the block shown in Figure 2, add:
// Add some functional logic
assign led_A = sw_A; // Add a non-inverting buffer assign led_B = ~sw_A; // Add an inverter
A ‘*’ after the filename in the tab above the editor indicates that you have not saved the file. Click the file save icon in the workspace panel to save your work.
We need to map the name of a variable such as ‘sw_A’ to a pin on the FPGA, this is effected using the constraints file ‘Nexys-4-DDR_MSc_Fragment_1.xdc’. In the “Sources” panel you will see a “Constraints” heading and under that the name of your constraint file e.g. Nexys-4-DDR- MSc_Fragment_1.xdc’. Double click on this source file to allow viewing and editing within the workspace panel. The file will contain some introductory comment lines (comments start with the symbol #) and then series of lines that define pin connections. Here are some examples:
## Switches
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {sw_A}]; set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sw_B}]; set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sw_C}]; set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {sw_D}];
and
## LEDs
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {led_A}]; set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {led_B}]; set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {led_C}]; set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {led_D}];
and
##Buttons
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {BTNU}]; set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {BTNL}]; set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {BTNR}]; set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {BTND}];
I originally downloaded this file from the Digilent repository and renamed the pins for this document. You may obviously call the pins any name you choose, but the Verilog input and output parameters must have matching names.
The way to understand this file is that sw_A in your Verilog source will be connected to pin J15 on the Artix-7 FPGA. This is the pin that is attached to the wire that connects to the switch on the board. Likewise sw_B in your VHDL will be connected to pin L16. There is some other information given (e.g. the voltage I/O standard that should be configured) but you don’t need to worry about that. The boards has an enormous number of connections that can deal with networking, video displays, audio, etc. It would be confusing to use all of them in your design so most of the lines in the XDC have been left commented out (starting with a #) so that you don’t need to reference them in your designs. You will also notice that we have only uncommented half of the available LEDs and switches to keep our initial design small. You can reinstate the remainder later as your design becomes more complicated.
4.1 Generating a schematic of your Verilog
In the “Flow Navigator” (the left-vertical panel) find the RTL Analysis option and click on Schematic.
This will give a graphical display of your design:
RTL stands for Register Transfer Level. This is a higher level abstraction used for hardware
design and is considered a mid-point between behavioural modelling as loved by computer
scientists and the gate-level structural modelling derived within the Digital Design module
finite state machine design lectures. You will note that the schematic diagram is closely
correlated with the desired specification illustrated in Figure 2. So all we have really achieved
is to replace a (possibly complex) circuit diagram with a few lines of textual entry representing
a digital circuit.
However, sometimes a “Critical Messages” pop-up will appear. In general, warning may be
ignored if you have carefully considered them. But adding the word ‘critical’ implies that
these are too serious to ignore. For example, a typical pop-up might look like:
At this point your Google-fu takes over and you search using the message keywords plus ‘Vivado’. Alternatively, you take intuitive guesses. Click on the “Messages” tab of the Results Area:
You will notice that each of the errors includes a line number in the constraints file (line 113, 114, 119, 120 in this illustrative example). A quick examination that these four lines refer to variables ‘Set_Button’ and ‘Reset_Button’ which do not appear in the parameter list of your Verilog file. Thus you have two alternatives: a) Comment out the offending lines in the constraint file, or b) add the two variables to the parameter list of the Verilog source file and define the pins as input. I chose to do the former.
When you make a change, a message such as ‘Elaborated Design is out-of-date – Reload’ will appear on a yellow band near the top of the screen. Press ‘Reload’. Continue the process of reading warning messages, changing the design and reloading until all warning messages have been resolved.
4.2 Synthesizing the design to hardware
In the Flow Navigator (left-vertical panel) click on “Run Synthesis”. You will probably be given a dialog box to specify how you want to do the synthesis. Just accept the defaults by clicking on OK. Synthesis may take a little while to complete. Look at the status bar in the top right hand corner:
The green circle will keep rotating until the process is complete. On completion it will change to a tick:
Synthesis converts your Verilog source code into a generic hardware netlist. Implementation is the process that maps this netlist onto the fabric of the actual FPGA that you have chosen. After synthesis is complete you will be presented with a dialog box which asks if you want to carry out the “Run Implementation”. Click OK and OK again on the ‘Launch Runs’ pop-up.
Eventually an ‘Implementation Completed’ pop-up appears. Click on ‘Generate Bitstream’ and click OK and OK again on the ‘Launch Runs’ pop-up.
The processor will run for a long time showing the ‘Running write_bitstream’ status.
Eventually a ‘Bitstream Generation Completed’ pop-up should appear. Click OK, or higlight the ‘Open Hardware Manager’ button first and then click OK.
During Covid-19 restrictions, you will be expected to provide evidence that the bitstream has been successfully generated for your designs.
4.3 Programming the Nexys 4 DDR Hardware
If you have access to hardware within the laboratory, the following stages may provide educational benefit. Make sure that your FPGA board is plugged into the computer USB port and is switched on. Scroll to the bottom entry on the ‘Flow Navigator’ (bottom-left) and expand ‘Open Hardware Manager’. Click on ‘Open Target’ then ‘Auto Connect’ in the pull-down menu.
A series of warning messages will appear such as ‘WARNING: [Labtools 27-3361] The debug hub core was not detected.’ If you were implementing a proper professional design, you would have the option to insert additional hardware into your design (called a debug core) that would enable the design tools to read out the actual state of the FPGA during operation. As you program the FPGA you will see some warnings saying that the tools haven’t been given a debug core. You can ignore these warnings.
Click ‘Program device’ in the green band near the top of the screen. Click ‘Program’ in the ‘Program Device’ pop-up that appears.
You should be able to change the switch on the bottom right of the board and the two LEDs nearby will change state.
4.4 Ever-Increasing Difficulty Verilog Tasks
Congratulation, you have probably designed and programmed your very first FPGA device.
Your next task is to work through the whole design chain again using different project and source file names. Your personal development specification should be:
• Led_A should be connected to a non-inverting buffer driven from sw_A (already achieved).
• Led_B should be connected to an inverting buffer driven from sw_A (already achieved).
• Led_C should be connected to a 2-input AND gate driven from sw_A and sw_B.
• Led_D should be connected to a 2-input OR gate driven from sw_A and sw_B.
• Led_E should be connected to a 2-input Exclusive-OR gate driven from sw_A and sw_B.
• Led_F should be connected to a 4-input AND gate driven from sw_A through sw_D.
Note: You are only allowed to use the combinatorial logic ‘assign’ statement, AND gates (&), OR gates (|), inverters (~) and parenthesis.
Action 2: Demonstrate non-inverting buffers, inverters, 2-input AND, OR and Exclusive-OR and 4-input AND gates using Verilog and your Nexys 4 DDR board.
All switches will suffer from mechanical contact bounce. Thus the digital logic will detect multiple transitions when only one was intended. The usual way of de-bouncing a mechanical switch contact is to use an asynchronous set-reset flip-flop connected to two push-buttons. A clock signal is then obtained by alternatively pressing the two buttons. Derive the sum-of-products expression for an active-high, set-reset flip-flop. Introduce a new output signal to your Verilog source and the constraint file such as ‘Clk_Q’.
When you attempt to run through all the stages of the Vivado you will very likely discover that a ‘write_bitstream’ error may be flagged in the status window. Under the ‘Messages’ tab of the output widow a convoluted message appears such as:
‘[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: ‘set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]’. One net in the loop is Clk_Q_OBUF_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: Clk_Q_OBUF_inst_i_2.’
This error message basically translates as ‘never attempt what you are doing – it is like disconnecting the air bags and anti-lock braking in your car’. However, we will ignore the sound advice and add the text ‘set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets]’ to the last line of the ‘Nexys-4-DDR-MSc_Fragment_1.xdc’ constraint file. Save the constraint file, press ‘Reload’ in the green bar near the top of the screen and click through any green triangles remaining in the ‘Flow Navigator’ (left-vertical) panel. You should be able to successfully test the clock de- bounce circuit on your Nexys 4 DDR board by alternatively pressing the top and then the bottom of the five buttons.
Action 3: Implement an asynchronous, set-reset flip-flop such that a de-bounced clock signal may be obtained from the upper and lower push-buttons. Learn how to deal with the critical error messages generated.
4.5 Ever-Increasing Difficulty Verilog Tasks – Synchronous Finite State Machines
At this stage, you have to design the transition logic of your synchronous finite state machine, starting by considering the specification.
The specification is possibly the most critical piece of information required by the engineer. In many cases this may not be completely specified, may be conflicting or may even be erroneous – the role of the engineer is to overcome these issues in conjunction with the customer.
Hopefully, the specification for this Digital Design module assignment is reasonably complete. You have been emailed a unique personal specification of the machine you are about to design. Transcribe this specification into your field note book.
My own preference is to start with a black-box diagram listing the inputs on the left, outputs on the right and any master clock at the bottom. You will obviously need to add arrows and clock symbols to your version of the documentation.
Order of Allowed States
Hence Unallocated States
Output active on state number
Inputs
Outputs
Black Box (FSM)
Clock
Read the specification again (from the assignment sheet) and extract the names of the input and output variables. The word ‘synchronous’ tells us there will always be a ‘clock’ signal. How many input variables are mentioned (names)? How many output variables are mentioned (names)? Draw them on the black box in your documentation. Do not be concerned about making mistakes, you can always start again later.
4.5.1 First-Guess State Diagram
The specification may be enough to allow the designer to construct a first-guess state diagram. This will almost certainly not contain any unallocated states introduced as a result of the implementation or any mention of the code assignment. Read the specification again and see if you can identify the number of states required and hence the number of circles on the state diagram. Have a go at generating the state diagram ….
SSSSSSSS
With most real-world designs, the interaction between states is quite complicated and it is easy to miss off a transition. The State Table is used as a safety check to identify any missing transitions. For this design the State Table is trivial – but add it to your documentation anyway.
What must you always remember to add to such diagrams?
Present State
Next State
Present Output
S
S
The above steps require no knowledge about digital systems and are simply graphical and tabular descriptions of a system.
4.5.2 Preliminary Design Step
Next, we have to start thinking about how we implement the finite state machine.
How many Secondary State Variables (feedback paths) do we need ? How are you going to describe these steps simply and concisely?
Use the appropriate equation here
Having decided how many Secondary State Variables there will be in a practical implementation, we can assign a unique binary code to each of the states. Unusually, we are going to use some output logic in this design, so we can assign a pure binary code to the state numbers.
State
Assigned Code Qd Qc Qb Qa
S0
0000
S1
0001
S2
0010
S3
S4
S15
1111
4.5.3 First Re-Write of State Diagram and State Table
Following the decision to use 2N states in the machine, there will almost certainly be some unallocated states appear that were not there in the initial specification. We do not yet know what to do with these as the specification tells us that we must route them in order to minimise the total amount of logic used. So all we can do is to redraw the State Diagram with ‘flying’ arrows for the transitions from the unallocated states and entering ‘unknown’ within the State Table destination column. It is a good idea to additionally include the code assignment within the circles at this stage. By the time you have finished the design, there will be three, or more, state diagrams revealing different stages of development.
SSSSSSSS
SSSS
Unallocated states introduced during the practiacl implementation
This time, enter the assigned code as well as the required outputs inside the states
We can re-write the State Table.
Present State Next State
Present Output
S0 S
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
The State Table will now have 2N entries, but the destination of some transitions will be unknown
4.5.4 Transition Table
The Transition Table will have 2N entries and will contain all the information required to derive the transition logic. Remember, the structure of the machine will look like:
Inputs (Primary State Variables)
X (t) Y(t)
Y(t1)
Y(t) Z(t)
Outputs
Transition Function
State Memory
Output Function
Feedback Paths (Secondary state Variables)
This state assignment, combined with the State Table, can be turned in to the Transition Table and then the Transition Function. However, we first need to know which type of state memory element will be used and its alternative form of the transition table.
For this assignment D-type flip-flops will be used with the following alternative form of the transition table :
The transition table can be derived :
Qn
Qn+1
Dn
0
0
0
1
1
0
1
1
Current State
Next State
Next D-Inputs
State
Qd
Qc
Qb
Qa
State
Qd
Qc
Qb
Qa
Dd
Dc
Db
Da
S0
0
0
0
0
S1
0
0
0
1
S2
0
0
1
0
S3
0
0
1
1
S4
0
1
0
0
S5
0
1
0
1
S6
0
1
1
0
S7
0
1
1
1
S8
1
0
0
0
S9
1
0
0
1
S10
1
0
1
0
S11
1
0
1
1
S12
1
1
0
0
S13
1
1
0
1
S14
1
1
1
0
S15
1
1
1
1
For each of the unallocated destinations insert a variable such as Ad, Ac, Ab, Aa, Bd, Bc, etc. as these are currently unknown but critical to the correct operation of the machine.
4.5.5 Extraction of Transition Logic
Next, we must extract the logic required to drive the D-inputs using four, 4-variable K-maps. Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Da Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Db Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Dc Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Dd
The next stage is where the fun really starts ! We want to minimise the logic used in order to implement the above transition functions. Traditionally this is achieved by using the largest
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00 01 11 10
00 01 11 10
grouping of 1, 2, 4, 8 or 16 implicants. So let us make a ‘blind’ attempt at this (do this in pencil as there will be lots of erasing):
Qb,Qa
The above K-map represents the transition logic required for input Da Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Db Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Dc Qb,Qa
Qd,Qc
The above K-map represents the transition logic required for input Dd
Check that the states to which the not-allowed states will transit to are allowed. For each of the groups of variables (such as Ad, Ac, Ab, Aa) replace the variable with a ‘1’ if a K-map group has enclosed it and a ‘0’ if it has not. These four bits tell you the destination of the transition. For example, if none of the K map groups enclosed variables Ad, Ac, Ab, Aa, the destination would be
Qd,Qc
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
0000. However, 0000 corresponds to state S0 which is an unallocated state and this banned within the specification. Similarly, if the K-map groups enclosed variable Ad, but not Ac, Ab, Aa, the destination would be 1000, or S8.
So extracting the next state we obtain the following :
State A goes to State State B goes to State State C goes to State State D goes to State State E goes to State State F goes to State State G goes to State
(OK / Not OK) (OK / Not OK) (OK / Not OK) (OK / Not OK) (OK / Not OK)
(OK / Not OK) (OK / Not OK)
It is very probable that an unallocated state will transit to another unallocated state (which is not allowed in the specification). So we must use a large dollop of common sense to see if there is an alternative solution. Your design guidance will be to reduce the size of an enclosing group first and then as a last-resort increase the number of groups (this will increase the number of AND gates in your circuit). You may need to iterate round this design loop multiple times.
The total system minimisation stages implemented above are much easier to deliver than to describe using words and algorithms. Thus the assessors will be looking closely at your attempts to describe the above stages in a clear and logical manner.
When this design stage is complete, extract the sum-of-product expressions for the transition logic from the K-maps.
During testing of the circuit, it will be necessary to consult the final State Diagram. Re-draw this for the third time showing the destination of all the un-allocated states.
SSSSSSSS
SSSS
Unallocated states introduced during the practiacl implementation
Da =
Db =
Dc =
Dd =
Take your four transition logic equations such as (these are deliberately erroneous):
D0Q2.Q1Q3.Q1Q0
D1 Q2.Q1.Q0 Q3.Q1.Q0 D2Q3.Q1Q2.Q1.Q0Q3.Q1.Q0 D3Q3.Q2Q3.Q0Q2.Q1Q1.Q0 Z Q3.Q2.Q1.Q0
Four equations are assumed to be the inputs to D-type flip-flops, whilst the last equation is assumed to be combinatorial. We already know how to implement the combinatorial logic e.g.:
assign Z = Q3 & Q2 & ~Q1 & ~Q0; // Combinatorial Output Logic (Z)
The next task is discover how to implement positive edge-triggered flip-flops. This is achieved by using an ‘always’ block, one that always executes and is delimited by ‘begin’ and ‘end’ statements. An always block should have a sensitive list or a delay associated with it. The sensitive list is the one which tells the always block when to execute the block of code, in this case the positive edge of the clock signal ‘Clk_Q’. The @ symbol after the reserved word ‘always’, indicates that the block will be triggered ‘at’ the condition in parenthesis after symbol @.
always @(posedge Clk_Q)
begin
Q0 <= (~Q2 & ~Q1) | (~Q3 & ~Q1) | (~Q0); Q1 <= (~Q2 & ~Q1 & Q0) | (~Q3 & ~Q1 & Q0); Q2 <= // Relevant statements
Q3 <= // Relevant statements
end
You will notice that two types of assignment operator have been used, ‘=’ and ‘<=’. For combinational logic a "=" was used for an assignment, whereas within the sequential block a "<=" operator was used. Formally, a "=" is known as a blocking assignment and "<=" is a nonblocking assignment. A "=" executes code sequentially inside a begin-end construct, whereas a nonblocking "<=" executes all the statements in parallel. For the case of Assignment 1, a parallel, or nonblocking, arrangement is required.
You will also have to modify the output port parameter list in the first few lines of the module by adding a ‘reg’ statement, e.g.
module MSC_Digital_Design_Synchronous_FSM( input JAM_A,
input JAM_B,
input JAM_C,
input JAM_D,
input JAM_Enable,
output reg Qa,
output reg Qb,
output reg Qc,
output reg Qd,
output Z, // etc,
Action 4: Take the constraint file such as ‘Nexys-4-DDR-MSC_Synchronous-FSM.xdc’ and ensure the names associated with pins are the same as your design variable names. Start a complete new project and include this new constraint file. Implement and test the allowed states and output logic of your original synchronous finite state machine design. You will require the asynchronous set-reset flip-flop to de-bounce your clock signal.
4.6 Ever-Increasing Difficulty Verilog Tasks – Synchronous Finite State Machines with Load Capability
You need the capability to effectively force the machine into all sixteen states in order to verify its behaviour. When implementing the design on an FPGA you need the equivalent functionality that will be obtained by setting the switches on the board to ‘jam’ data into the bistable elements.
Edit the constraint file and rename the first five switches something like Jam_A, Jam_B, Jam_C. Jam_D and Jam_Enable. You are going to modify your transition equations such that when Jam_Enable is high, the contents of Jam_A will be transferred to Qa, the contents of Jam_B will be transferred to Qb, etc. following a clock pulse. Every AND gate within your transition logic will contain a Jam_Enable term, for example:
Qa <= (~Qc & ~Qb & ~Jam_Enable)|(~Qd & ~Qb & ~Jam_Enable)|(~Qa & ~Jam_Enable)|(Jam_A & Jam_Enable);
Recompile the Verilog, generate a new bitstream and test the functionality of all the states of your synchronous finite state machine using the Nexys 4 DDR board
Action 5: Add a capability to synchronously load test data entered on switches into your Assignment 1 finite state machine. Implement and test the allowed states, the not- allowed states and the output logic of your original synchronous finite state machine design. You will require an asynchronous set-reset flip-flop to de-bounce your clock signal.
Asynchronous Finite State Machine Design Assignment (Part 2) 5.0 Asynchronous Finite State Machine Design Process: Electronic Lock
Start the design by specifying the five keys to be pressed in sequence. This unique personal sequence will have been emailed to you.
5.1 State Diagram
You are now in a position to draw an initial State Diagram. However, there are many inputs to this machine and some form of shorthand nomenclature might be appropriate. One way of achieving this is to pre-process some of the inputs. For example, we might end up with three different types of pre-processed functions:
k7 represents key number seven pressed and no other key.
Keys 1
Key 2
Key 3
Key 4
Key 5
k 7
represent any key other than key seven, or a combination of keys pressed.
0 represents no keys pressed.
Your state diagram will probably include six or more states. This requires three secondary state variables that could be conveniently implemented by using three, or more, output pins - perhaps Qa, Qb and Qc. The output used to control the door solenoid, Z, may be implemented using combinatorial output logic ( logic).
AB
CD
FE
Do not forget:
To add the fraud-protection transitions.
To add the "reset" transitions.
To label the transitions.
To label the output conditions.
It will be noted that with ten key inputs, one door switch, a reset input and three internal states, that a complete flow, or transition table would contain 32768 entries. A more compact form of the flow and transition table will therefore be required. For this particular case, there are so many inputs and therefore potential transitions, that the generation of a flow table within your field note books may not be appropriate. However, if you were designing this machine in the workplace, you would undoubtedly adopt some form of computer assisted documentation (e.g. a spreadsheet) to ensure that every possible transition is accounted for.
5.2 Code Assignment
A suitable unique code must be assigned to every state. The transitions between states should be associated with single-bit code changes. Perhaps use a zero-hot, one-hot, two-hot strategy here with the minimum number of secondary state variables, or a Gray code – whichever proves to be the simplest. The code assignment will be as follows:
State
Qe
Qd
Qc
Qb
Qa
A
B
C
D
E
F
G
H
5.3 Second Iteration of State Diagram
The State Diagram can been redrawn including the codes assigned to the states as well as the output condition. This process will undoubtedly reveal multi-bit changes that must be addressed in a suitable manner.
AB
CD
FE
It is frequently necessary to insert additional, dummy-states at this stage in order to maintain the requirement for single-bit transitions between states. This will be a particular problem for the fraud transitions but not for the reset transitions (as all states will have a reset transition back to the safety state and so the machine rapidly flows through any state it encounters back to the reset state)
5.4 Extraction of Implicants
All conditions that will lead to a "1" in the feedback variable for the next state are associated with an active-term (true) in the transition equations. However, we need to be able to expand the shorthand descriptions used earlier.
e.g. k7
k 7
0
The fraud condition will cause you the most ‘brain ache’. Remember that there are 8 choices of one fraudulent key being pressed, 10x9 choices of two fraudulent keys being pressed, 10x9x8 choices of three fraudulent keys being pressed, etc. Overall, there are more than 1.6 million terms to be processed in this design per fraud transition. You will perform some fundamental Boolean minimisation operations on this problem and reduce the dimensionality to just eight terms per SSV, per transition.
Next, write down the non-minimised (implicants) equations for the feedback variables. Qa =
Qb =
Qc =
5.5 Extraction of Prime Implicants
It is essential that all prime implicants are included within the transition equations. Remember that
the prime implicants are the largest groups that can be circled on a K-map.
It is generally impossible to draw K-maps corresponding to more than six variables. Thus, the trick is to remove all the common variables from each transition equations in turn. The remaining variables may then be reduced to their prime implicants form using K-maps, e.g.
Qa = (Common Terms/Variables).(Remaining Variables) Qa =
Qb =
Qc =
Having extracted all the prime implicants, your job is to code these three equations using Verilog. If your device reverts back to the idle state (State A) as the correct keys are pressed, then you have almost certainly failed to include all the prime implicants within your transition equations and you have just discovered the joy of race hazards.
Action 6:
Design the transition logic for the asynchronous lock implementation, taking particular care to mitigate static race hazards. Your design should incorporate features to eliminate key bounce whilst still rejecting attempts by hostile users to unlock the door. Implement and test this design on the Nexys 4 DDR simulator (and board if available). You will need to generate a further copy of the constraint file with the input and output names matching your design. You may use output logic for the solenoid drive signal.
5.6 Remainder of tabular methods of minimisation
Sometimes you have more than six remaining variables that need to be minimised and techniques other than K-maps have to be used. So let us remind ourselves of typical first year undergraduate material. We will start with an outline of an algorithm that could be implemented manually or in a language such as Matlab.
Potential Logic Minimization Algorithm
One possible algorithm for algebraic minimization of a logic equation might be as follows. We start with a canonical sum-of-products equation containing N product terms (or probably rows separated by a ‘+’in your case). For each of the N product terms:
Define a reference term and compare this to every other product term in the equation.
If it varies by only one variable, then include this term (excluding the term that varied) into
the next stage of the process. e.g. A.B.C A.B.C will be included as A.B in the next stage.
If it varies by only more than one variable, then ignore this comparison.
If there is no comparison between the reference term and any other term, then transcribe the reference term into the next stage of the process.
After all comparisons have been made, remove any repeated terms. Repeat the above stages until no further simplifications are possible.
Obviously you can adapt the algorithm to reduce the number of comparisons needed by adding extra constraints and rules.
Example using this simple algorithm
Start with a typical equation T A.B.C.D A.B.C.D A.B.C.D A.B.C.D A.B.C.D For your problem, this would be written as five rows and each row would contain fifteen terms instead of the four used here.
Take the first reference term, A.B.C.D , and perform comparisons to all other terms yielding A.B.D.C C B.C.D.A A.
Take the second reference term, A.B.C.D , and perform comparisons to all other terms yielding A.B.D.C C B.C.D.A A.
Take the third reference term, A.B.C.D , and perform comparisons to all other terms yielding B.C.D.A A A.B.D.C C .
Take the fourth reference term, A.B.C.D , and perform comparisons to all other terms yielding B.C.D.A A A.B.D.C C .
Take the fifth reference term, A.B.C.D , and perform comparisons to all other terms. As there is no comparison we transcribe A.B.C.D to the result.
Now combine the results of the above stages together (using the OR construct) while removing the variables that have changed.
T A.B.D B.C.D A.B.D B.C.D B.C.D A.B.D B.C.D A.B.D A.B.C.D Remove any repeated terms.
T A.B.D B.C.D B.C.D A.B.D A.B.C.D
Repeat the process again (shown as a single line this time).
T AA.B.DB.CC.DB.CC.DAA.B.DA.B.C.DB.DB.DB.DB.DA.B.C.D Removing repeated terms reveals the result T B.D A.B.C.D
This process will extract all the prime implicants of your transition equations.
5.7 Alternative code assignment strategies
By this stage, you will have noted that it is the fraud transitions that cause you the most work. By ensuring that the fraud transitions terminate at the zero-hot code assignment state, all related terms vanish from your equations.
Processed Inputs ?
ABCEGI 00000 00001 00010 00100 01000 10000
BDFH 00011 00110 01100 11000
Outputs:
Qe, Qd, Qc, Qb, Qa
Thus you can trade the complexity of each equation against the number of feedback paths and equations. There is no correct solution, only a differing set of compromises.
Expectation: There are obviously many ways of implementing the electronic lock. The end result should be perhaps three-to-nine hours of preparatory work and Verilog entry followed by as little as two hours using the Nexys 4 DDR simulator (and board if available) for testing the final product in the laboratory.
6.0 Simulation
Very often the hardware implementation is not available until the latter stages of a project. Thus the digital designer will be forced to test their code using a software model – a process called simulation. In addition, a competent engineer will attempt to ‘cover’ every possible eventuality within a machine – a term loosely called ‘coverage’. This may be far simpler to achieve in software, or simulation, that in hardware.
Please instantly dismiss any ideas that simulation is easy. You will rapidly discover that 70% to 80% of the design time will be spent on the simulation aspects. Your assignments award a significant fraction of the available marks for demonstrating that you have simulated the design and presented the results in a manner that a non-technical lawyer can comprehend.
This is the most important, useful and difficult part of the assignment to perform. A simulator requires both a description of the equivalent circuit under-test and a set of stimulus simulation input values. For these assignments you are going to use a text file based input of stimulus test vectors – you will find that this is the ‘industry preferred’ method of simulating large designs and is a more defendable method of protecting yourself in a court-of-law against negligence claims.
6.1 Simulation Hierarchy
The simulation process will conceptually appear as shown in Figure 3. You will write a Verilog simulation module, such as ‘module Fragment_1_Test_Bench();’ and define it to be the highest level within a hierarchy of modules.
Highest-Level Verilog Module ()
sw_A sw_B sw_C sw_D
Inputs to Module defined as ‘reg’ at highest-level
led_A led_B
led_C led_D led_E
led_F
Outputs from module defines as ‘wire’ at highest level
Verilog Module
Figure 3: Verilog simulation module hierarchy Achieve this by clicking on the ‘+’ symbol within the ‘Sources’ pane.
An ‘Add Sources’ panel will appear. Highlight the ‘Add or create simulation sources’ button and then click ‘Next’. Click the ‘Create File’ and add a filename such as ‘Fragment_1_Test_Bench’.
You can enter the signal names that you wish to use. However, at the highest level, signals that will be used as inputs to lower-level modules must be defined as storage registers using ‘reg’ and signals that will be used as outputs from lower-level modules must be defined as wires using ‘wire’.
Set the top level of the hierarchy by right-clicking on the simulation file name within the sources pane and selecting ‘Set as top’. Three green dots will appear to show the position at the top of the hierarchy.
A first attempt at writing a simple test bench might appear as follows (please read the comments)
module Fragment_1_Test_Bench(); // At highest level not parameters are passed
wire out_A;
wire out_B;
wire out_C;
wire out_D;
reg Signal_1;
reg Signal_2;
// At highest-level outputs from other modules // appear as wires
// At highest-level inputs to other modules
// appear as registers
// Most of your code could appear within an ‘initial’ block
initial begin
//Initialize clock
Signal_1 = 0;
Signal_2 = 0;
#10 Signal_1 = 0;
#10 Signal_1 = 1;
#10 Signal_1 = 0;
#10 Signal_2 = 1;
#10 Signal_1 = 1;
$finish;
end
// Instantiate your lower-level modules
Test_Fragment_1 PhilModule(Signal_1, Signal_2, out_A, out_B, out_C, out_D); endmodule
Note that here ‘Test_Fragment_1’ is the file that contains your source code that will be loaded onto the board and ‘PhilModule’ is any random name to keep the software happy.
You have the task of teaching yourself enough Verilog in a few minutes in order to be able to thoroughly simulate the design. It is suggested that you write simple linear, procedural code (avoiding loops, conditional statements, sub-routines, etc.) and this stage. For many simulations, the Verilog statements may be included within a ‘initial-begin-end’ block. Signals may be asserted true, or false. Time delays may be inserted using the ‘#10’, where the number represents a multiple of the basic timing rate (set up as a default value of 1 ns by Vivado). You will notice that you must include an instantiation of any Verilog lower-level modules that you intend to use.
Helpful Hint: Only add perhaps five lines of code at a time and then sort out the simulation errors introduced.
Click on the ‘Run simulation’ then ‘Run behavioural simulation’ within the left-hand flow navigator pane. The results are presented in a waveform format – you will have to appropriately scale the timing to view these.
Zoom to full view
Stop – Think. By this point, you have obtained a very pretty timing diagram of the output of your design. Only you will be able to understand it – a lawyer will tear you apart! You need to find a better way!
The first approach is to expand the signals, such that you can read off the data at the cursor. The yellow cursor is initially parked at the left-hand edge of the window and may be dragged with the mouse.
2. Zoom in
1. Expand the signals
3. Click on a signal and use the keyboard cursor keys to move the yellow cursor between waveform edges – read-off the signal values.
Stop – Think. You have obtained a slightly more useful simulation of your design. You are still the only person able to understand it – a lawyer will still tear you apart! You still need to find a better way!
You need to start thinking about verification rather than simulation. This probably involves the final state diagram, annotated waveforms and printed textual documents. The functionality of Verilog may be extended by adding textual write operations.
The first command of use is that of ‘$monitor’. This allows the state of signals to be reported to to the Tcl Console every time they change state. For example, the C language like command
$monitor ("Signal_1 = %b, Signal_2 = %b, Out_A = %b, Out_B = %b, Out_C = %b, Out_D = %b",Signal_1,Signal_2,out_A,out_B,out_C,out_D);
added at the top of the ‘initial’ block might yield a console output such as:
You can start adding ‘$display’ commands to annotate the test report. Typically, you might add a series of messages such as:
$display("State 0 should transit to state 9");
Thus we can get an output on the console a mixture of variable values and constant textual
expectations such as:
Starting Simulation
Test normal state transitions
Force into State 0, LEDs = 0000 Z = 0 Clocked to State 5, LEDs = 1010 Z = 0 Clocked to State 7, LEDs = 1110 Z = 0 Clocked to State 8, LEDs = 0001 Z = 0 Clocked to State 9, LEDs = 1001 Z = 0 Clocked to State 11, LEDs = 1101 Z = 0 Clocked to State 12, LEDs = 0011 Z = 0 Clocked to State 13, LEDs = 1011 Z = 0 Clocked to State 3, LEDs = 1100 Z = 0 Clocked to State 4, LEDs = 0010 Z = 0 Clocked to State 5, LEDs = 1010 Z = 0
Test not-allowed state transitions Force into State 0, LEDs = 0000 Z = 0 Clocked to State 5, LEDs = 1010 Z = 0
Force into State 1, LEDs = 0001 Z = 0 Clocked to State 7, LEDs = 1001 Z = 0
You can obviously improve on this approach significantly! Instead of writing to the console, it will probably appease a lawyer more if the data is written to a date-stamped file. First open a file with:
integer File_Handle; // A 32-bit integer is required for any handle to a file
File_Handle = $fopen(“DD_Lab2_Verification_File.txt"); // declare output file
$fwrite (File_Handle,"Signal_1 = %b, Signal_2 = %b, Out_A = %b, Out_B = %b, Out_C = %b,
Out_D = %b\n",Signal_1,Signal_2,out_A,out_B,out_C,out_D);
$fclose(File_Handle);
You will notice that ‘$fwrite’ uses a similar syntax to the C print statements that you are used to. By this stage you in a position to write a script containing several thousand lines of code that will automatically test the machine against the expected behaviour of the state diagram.
A useful link is: https://www.xilinx.com/Attachment/Xilinx_Answer_53776_verilog_simulation_testbench_ver17.pdf
Hopefully, you are now in a position to deliver the assignments.
Personal Development Checklist for Key Skills
Important Note: Please consider the majority of these key skills as worthwhile revision for the module examination. Anything that appears in this document is as likely to appear in an examination as lecture material.
Comment
Self- Verified
Action 1: Download the latest Xilinx Design Suite HLx Editions (e.g. 2019.2 at https://www.xilinx.com/support/download.html).
Action 2: Demonstrate non-inverting buffers, inverters, 2-input AND, OR and Exclusive-OR and 4-input AND gates using Verilog and your Nexys 4 DDR board.
Action 3: Implement an asynchronous, set-reset flip-flop such that a de-bounced clock signal may be obtained from the upper and lower push-buttons. Learn how to deal with the critical error messages generated.
Action 4:
Take the constraint file such as ‘Nexys-4-DDR-MSC_Synchronous- FSM.xdc’ and ensure the names associated with pins are the same as your design variable names. Start a complete new project and include this new constraint file. Implement and test the allowed states and output logic of your original synchronous finite state machine design. You will require the asynchronous set-reset flip-flop to de-bounce your clock signal.
Action 5: Add a capability to synchronously load test data entered on switches into your Assignment 1 finite state machine. Implement and test the allowed states, the not-allowed states and the output logic of your original synchronous finite state machine design. You will require an asynchronous set-reset flip-flop to de-bounce your clock signal..
Action 6:
Design the transition logic for the asynchronous lock implementation, taking particular care to mitigate static race hazards. Your design should incorporate features to eliminate key bounce whilst still rejecting attempts by hostile users to unlock the door. Implement and test this design on the Nexys 4 DDR simulator (and board if available). You will need to generate a further copy of the constraint file with the input and output names matching your design. You may use output logic for the solenoid drive signal.
Introduction
Appendix
Remote Access to Vivado HLx
This document is aimed at those who do not have sufficient computer resources at home. The process will be to log on to a machine in the Gisbert Kapp building, run the Vivado Hlx software, generate simulations and bit streams on that computer.
This will never be as quick, or as pleasant, as sitting in the computer cluster itself. However, if you find easier ways, then please write it up and I will post your document on Canvas.
Remote Access to a Gisbert Kapp Cluster
If you have not already done so, follow the guidance on https://universityofbirmingham.service- now.com/itportal?id=uob_kb_article&sysparm_article=KB15128&sys_kb_id=47463c2adb3 b1450e583e5ff4b9619c0&spa=1
You will need VPN access to the University of Birmingham and this is normally achieved by installing “BIG_IP Edge Client” on your local machine. (Students, please see KB15126 (Windows/macOS) or KB15154 (ChromeOS))
Run this client and log-in with your University user name and password. You will need a two-factor authentication system such as a phone and this stage normally takes me twenty minutes before I am allowed access.
Run https://remoteclusters.bham.ac.uk which will result in an introductory screen such as:
Scroll down to Gisbert Kapp – NG22, 337 or 418 and click on that item.
Click on any machine that has the ‘Windows’ symbol on it. These are free machines that may be used remotely. In the top-right ribbon, you will see a square with an arrow in it – click on this.
Once you choose to connect to a PC, it will be reserved for you and you will have 3 minutes to connect. If you don't do so within this time the PC will become available for use by someone else.
On the popup window which appears, click the 'Download' button. Your browser will then download an RDP file called 'connect.rdp'.
When this file is downloaded, double click on it to open it. If you're asked to connect again, click 'Connect' (Windows) or 'Continue' (macOS) on the window which appears.
You will then be asked to login to the computer. Use your University email address to login. If this doesn't work, login using ADF\username, for example ADF\BloggsJ
After a few seconds you will be connected to the device.
Workspace Preparation
Having read the pre-lab documentation, I knew that I needed a storage area on the network drive which I called ‘Vivado’. I then created sub-directories such as ‘Assignment_1’ and ‘Assignment_2’.
I copied the constraint file from Canvas into these areas (*.xdc) and also made copies ready to be modified such as ‘Assignment_1.xdc’.
I also needed the board file, so downloaded the ‘vivado-boards-master.zip’ file from Canvas and extracted it into the network ‘Vivado’ directory.
Running Vivado
I started to type in ‘Viv’ into the Windows start menu and then clicked on ‘Vivado 2018.2’ to start the application (which takes many seconds to start).
To get round the lack of administrative privileges, go to the ‘enter command’ box at the bottom of the screen and enter
set_param board.repoPaths X:/Vivado/ // Change the drive letter
I then clicked on ‘Create Project’ and followed the pre-lab instructions and saved the projects and files on the network drive using a project name such as ‘Project_Play_1’. I added a source file such as ‘Verilog_Play_1’ and added the code from the pre-lab sheet. I then modified the constraint file to make sure that the name of my single switch and two LEDs used matched the names contained in the Verilog file.
I spent a few minutes noting the error messages displayed in the ‘Console messages’ panel until I had a successful bitstream generated. I searched for ‘*.bit’ and found the file hiding in
X:\Vivado\Project_Play_1\Project_Play_1.runs\impl_1\Verilog_Play_1.bit
If you do have access to a hardware board, many of them can be programmed using a small capacity USB stick formatted as FAT32.
Logging Off
Once you've finished using the remote computer, you should always log off. Failing to do so may prevent other people from using the device until it is rebooted.
In order to log off, click on the start menu then the small user icon. Select 'Sign Out' from the popup that appears.