SOF108 COMPUTER ARCHITECTURE
TUTORIAL 7 – Memory Hierarchy -I
1. Consider a direct mapping with the following information: 24-bit addresses, 64Kbyte cache, 16 byte cache lines. Identify how many bits are required in the tag, line and offset fields.
Tag field will have 8 bits Line field will have 12 bits Offset field will have 4 bits
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2. Consider a associative mapping with the following information: 24-bit addresses, 128Kbyte cache, 64 byte cache lines. Identify how many bits are required in the tag and offset fields.
Tag field will have 18 bits Offset field will have 6 bits
3. Consider a 2-way set associative mapping with the following information: 24-bit addresses, 128Kbyte cache, 16 byte cache lines. Identify how many bits are required in the tag, set and offset fields.
Tag field will have 8 bits Set field will have 12 bits Offset field will have 4 bits
4. For the hexadecimal main memory addresses: 111111, 666666, BBBBBB, show the following information, in hexadecimal format:
a) Tag, Line, and Word values for a direct-mapped cache, using the following format.
b) TagandWordvaluesforanassociativecache,usingthefollowingformat:
c) Tag, Set, and Word values for a two-way set-associative cache, using the following format:
5. List the following values:
a) For the direct cache example below: address length, number of addressable units,
block size, number of blocks in main memory, number of lines in cache, size of tag
b) For the associative cache example below: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag
c) For the two-way set-associative cache example below: address length, number of addressable units, block size, number of blocks in main memory, number of lines in set, number of sets, number of lines in cache, size of tag
a) Address length: 24; number of addressable units: 224; block size: 22 = 4; number of blocks in main memory: 224-2 = 222; number of lines in cache: 214; size of tag: 8.
b) Addresslength:24;numberofaddressableunits:224;blocksize:22=4;numberof
blocks in main memory: 224-2 = 222; number of lines in cache: indeterminate; size
of tag: 22.
c) Address length: 24; number of addressable units: 224; block size: 22 = 4; number of
blocks in main memory: 222; number of lines in set: 2; number of sets: 213; number of lines in cache: 213 × 2 = 214; size of tag: 9.
6. A set associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K × 32 bits. Considering a byte addressable memory, design the cache structure and show how the processor’s addresses are interpreted.
The following answer is calculated based on the assumption of a byte addressable memory.
Block size = 4 x 16 bit words = 8 bytes = 23 bytes3 bit to encode which byte Cache size = 4096 words = 212 words × 2 bytes = 213 bytes
Number of cache lines, C = 213 = 210 = 1024 23
Associativity K = 2,
So, number of sets S = C/K = 1024 / 2 = 512 = 29 Set = 9 bits
Main Memory Size = 64K × 32 bits = 64 × 4 Kbytes = 256 Kbytes = 28+10 bytes = 218 bytes
Number of bits for the address = 18 bits (byte addressable)
Tag Set Offset: Byte
7. Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used.
a. How is a 16-bit memory address divided into tag, line number, and byte number?
b. Into what line would bytes with each of the following addresses be stored?
0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101
1010 1010 1010 1010
c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it?
d. How many total bytes can be stored in the cache?
e. Why is the tag also stored in the cache?
a. The block size is 8 bytes. So the number of bits required in the offset (byte) field can be calculated as: log2 8 = 3 bits
There are 32 lines in the cache. So the number of bits required in the line field can be calculated as: log2 32 = 5 bits
This is a byte addressable memory where the capacity of the memory is 216. So, the total length of the memory address is 16 bits. Therefore, the tag can be calculated as: 16- 3-5 = 8 bits.
The other way to calculate the tag is:
Number of blocks in main memory: 216 = 213. So, 13 bits are needed to address a
block in main memory. Note that for direct mapping the block address is formed by combining the tag and the line field.
There are 32 lines in the cache. So the number of bits required in the line field can be calculated as: log2 32 = 5 bits
So,tagsizeis: 13–5=8bits
The block size is 8 bytes. So the number of bits required in the offset (byte) field can be calculated as: log2 8 = 3 bits
b. 0001 0001 0001 1011 Line number 3 1100 0011 0011 0100Line number 6 1101 0000 0001 1101Line number 3 1010 1010 1010 1010Line number 21
c. It will include other addresses which belongs to the same block. Along with the contents of address 0001 1010 0001 1010, there are seven other bytes in the block (defined by the offset field):
d. Total number of bytes that can be stored in the cache = 32 × 8 bytes = 256 bytes
e. This is a direct cache mapping. So there are several blocks that can be mapped in to the same cache line. From the tag field, we can see that there are 28 = 256 blocks that can be mapped into the same cache line. The purpose of the tag is to differentiate between these 256 blocks that are mapped into the same cache line.
8. Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.
a. For the main memory addresses of F0010, 01234, and CABBE, give the
corresponding tag, cache line address, and word offsets for a direct-mapped
b. Give any two main memory addresses with different tags that map to the same
cache line for a direct-mapped cache.
c. For the main memory addresses of F0010 and CABBE, give the corresponding
tag and offset values for a fully-associative cache.
d. For the main memory addresses of F0010 and CABBE, give the corresponding
tag, cache set, and offset values for a two-way set-associative cache.
Note: For this answer the contents of different fields are provided in hexadecimal.
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