代写代考 ECE3375, Winter 2022

Analog-to-Digital Conversion
Prof. Leod ECE3375, Winter 2022
This lesson introduces analog-to-digital conversion. Some hardware implementations of analog-to-digital converters are discussed, and we describe how to inter- act with these peripherals in software.
In previous courses this unit covered integrating analog-to-digital converters, but this year we won’t. But

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— I don’t like deleting stuff from my notes. So instead, those sections are marked “optional”, won’t be covered in class, and you don’t need to learn it.

Analog-to-Digital Conversion
Most real-world information is analog. An analog signal vs(t) varies smoothly and continuously in voltage and time. This signal must be converted to digital in order to be processed by a microcontroller. For this reason, almost all microcontrollers have at least one analog- to-digital converter peripheral (“A/D” or “ADC”) built-in.
Definition: An analog signal is sampled if it is only measured at discrete time intervals ∆t (or measured and averaged over that inter- val).
Definition: An analog signal is discretized if the voltage amplitude is rounded to some multiple of the voltage resolution ∆V .
Definition: An analog signal is digitized when it is both sampled in time and discretized in amplitude.
Definition: A digital signal is binary if only two discretization levels (equivalent to 0 and 1) are used.
Technically, most ADC are actually analog-to-binary converters (or ABC?), as they take a single analog input and produce an n-bit binary output. But whatever… the name ADC is what everyone uses. A representation of sampled, discretized, and digital signal is shown in Figure 1.
• Time sampling is usually done in multiples of the CPU clock cycle.
Figure 1: Various representations of an analog signal (a sine wave). Top: The signal is sampled at a given time interval. Middle: The signal
is discretized into a given voltage increment. Bottom: The signal is fully digitized.

• Exactly how the voltage is discretized depends on the hard- ware implementation of the ADC, we will discuss some imple- mentations later.
A discretized analog signal can only be understood if the reference voltage, bias voltage, and data width are known. A given analog voltage V can be discretized into n bits as:
􏰂bn−1 bn−2 b0 􏰃
V = 2 + 4 +···+2n Vref +Vbias,
where bi is the value of digital bit i, Vref is the reference voltage (or scale voltage), and Vbias is the bias voltage.
• Note that in this definition, the “bias voltage” refers to the minimum voltage in the analog signal, as the sum of the bit values is strictly positive. 1
• Often this bias is removed before ADC, so Vbias = 0 V.
From the above expression it should be clear that the resolution
∆V of the discretized signal is:
∆V = Vref .
This is the smallest non-zero analog signal that can be represented innbits.WithatypicalreferencevoltageofVref =5V,discretizing asignalinton = 16bitsgives∆V = 76.3μV,whichisoftenwell below the noise threshold for a typical circuit. Consequently, ADC is rarely done with more than n = 16 bits of width. 2
1 Or the maximum voltage, if Vref < 0. 2 Eventhatisabitextreme—ifn = 8then ∆V = 19.5 mV which is already pretty small for most circuits. Digital-to-Analog Conversion The first circuit we will consider is an ADC turned on its head: a digital-to-analog converter (DAC). This actually takes a n-bit binary input and produces a digital output (so a BDC?), but in the micro- controller world anything that is not binary is considered analog. How does one convert a n-bit binary number into a single analog signal? • Contrary to what some of your classmates think, simply con- necting two or more wires together does not add the voltages together. • However currents do add together. • If bit m with value bm can be converted into a current propor- tional to 2mbm, then the sum of all these currents is representa- tive of the signal. The best way to switch between voltage and current is to use a resis- tor. Consider the resistor network shown in Figure 2. The mth input is Vref if the corresponding bit bm = 1, and 0 if bm = 0. Applying b0Vref b1Vref bn−2Vref bn−1Vref R 2−1R 2−n+2R 2−n+1R n-bit binary value into a voltage vout. ··· vout RL Kirchoff’s current law at the node vout, we have: out = 􏰈 (bmVref − vout) Figure 2: A resistor network for converting a RL m=0R 􏰆11n−1􏰇 Vn−1 + 􏰈2m vout=ref􏰈2mbm Rm=0 R m=0 This is kind of a mess, but it works: the output voltage vout is pro- portional to the binary number bn−1bn · · · b1b0. This isn’t a practical DAC, however, because the output voltage scales with the load re- sistance. Ideally we want the output voltage to depend only on the binary value, not on whatever load peripheral we have connected to the DAC. The simplest practical n-bit DAC uses an operational amplifier (op amp) to sum a set of n binary signals and act as a buffer to keep the 􏰂R 􏰃−1 n−1 v = +2n−1 V 􏰈2mb out R ref m L m=0 output voltage stable, independent of any load. The signal from bit m resistor 2−mR — as the resistance decreases with increasing bit, the current is that much larger. Those of you who paid close atten- tion in your electronics classes will recognize this as a particular implementation of a weighted inverting summer. 3 3 The word “summer” means a “circuit that performs summations,” not the season. Figure 3: An n-bit weighted-resistor circuit for DAC. The digital signal Q[n − 1, ..., 0] is converted to the analog output vout. Analyzing this circuit is straightforward, assuming you remember the principle of superposition. • Because of the operating principles of the op amp, the −’ve terminal is at essentially zero potential — as it is tied to the +’ve terminal by a virtual short circuit. • The current that flows from signal Qm = 1 is im = 2mvref /R. • Current cannot flow into the op amp, so all of the currents add and flow across the feedback resistor. The output is therefore: vout = −Ritot m=n−1 􏰂2mQm 􏰃 􏰈 Note that this is an inverting circuit, this is typically fixed by using a negative reference voltage vref . The weighted-resistor DAC circuit above can sometimes be prob- lematic because so many different resistances are needed. A simpler design uses only standard resistances R, 2R, and one resistance 3R. 4 This circuit is typically based on an op amp, as shown in Fig- ure 4. 4 The 2R and 3R resistances of course can be made from three R in series, of course. Figure 4: An n-bit ladder converter circuit for DAC. The digital signal Q[n − 1, ..., 0] is converted to the analog output vout. Qn−2 Qn−1 2R 2R Again, analyzing this circuit is straightforward. 7 • If only one input Qm is considered, and all other inputs are set to ground, the equivalent circuit for that input is shown in Figure 5. This occurs because the resistances were carefully chosen: Note that 2R ∥ 2R = R. • The equivalent resistance seen by Qm is 2R + 2R ∥ 2R = 3R, so the current is: 􏰂Qm􏰃 im= 3R Vref, where Vref is the voltage of binary signal 1. • The equivalent circuit for input Qm also makes it clear that any current which flows from signal Qm gets split in half at the node. • The half current that flows right towards the op amp will fur- ther be split in half each time it reaches a node for Qp (where m < p < n − 1). The current from signal Qm that reaches the −’ve terminal of the op amp is therefore: 􏰂Qm 􏰃Vref im,− = 2n−m 3R . • By Kirchoff’s current law, the total current reaching the op amp is just the sum of all the signals: Figure 5: Equivalent circuit by the principle of superposition for any input Qm in the ladder converter from Figure 4, when all other signal sources are replaced with grounds. V m=n−1 Q itot,−=ref􏰈 m 3R m=0 2n−m 8 • This current can’t enter the op amp, as the impedance at the input is almost infinite. Instead it must flow across the 3R resistor. The output voltage is therefore: = −V 􏰈 tot,− ref 2n−m 􏰂Q0 Q1 =−Vref 2n +2n−1 +...+ 4 + 2 . Qn−2 Qn−1􏰃 This is a digital signal, as it has 2n discrete voltage levels, and can only change in value when the inputs Qm change — and they are controlled by the system clock. However for a sufficiently fast clock (as is usually the case) and reasonably large n (as mentioned above, n = 8 is usually plenty), this signal is often indistinguishable from a true analog signal. Successive-Approximation Converters A successive-approximation converter is a robust circuit that does not require precision components, and that has a fixed conversion time regardless of signal magnitude. 5 A schematic of this device is shown in Figure 7. This circuit implements a binary search for the correct value that digitizes vs(t), by comparing the current estimate of that value (Q7, Q6, ..., Q0) to vs(t) using a DAC. • The first stage of this circuit allows the signal vs(t) to charge a capacitor. This is the “sampling and hold amplifier”. A timer control signal (tmr in Figure 7) is used to turn on and off the transistor switch. • From circuits class, you hopefully recognize that the voltage across capacitor CADC is: 􏰄 􏰂 t 􏰃􏰅 vADC=vs1−exp−R C , as long as the signal voltage vs(t) is fairly constant over the sampling time. • As t → ∞, vADC → vs, so a sample time is selected that is large enough such that vADC settles within the resolution limit of the signal voltage. • The next stage of this circuit is an open-loop op amp compara- tor. Because there is no feedback loop, the output saturates to 5 Actually this device is usually called a successive-approximation register, or SAR. vADC /Vref 1 verr = Vref /16 Figure 6: Example of using the sampling and hold amplifier from a 3-bit SAR ADC. If the signal is sampled for a time ts, then the error in the maximum sample (vs = Vref ) is half the resolution. Any signal with lower voltage (vs < Vref ) sampled for this same time ts will therefore have an even smaller error. Vref or 0 depending on whether the positive or negative input is larger. • Therefore, if vADC > vA, the output saturates to ground. If vADC ≤ vA, the output saturates to Vref .
Sampling and Hold Amplifier
C Figure 7: A rough schematic of a n-bit successive-approximation ADC.
Comparator
The “logic” part of the circuit is more complicated than a simple counter (and that is why I drew it as a block), it is responsible for performing the binary search. The logic circuit processes the output bit-by-bit, starting with the MSb and working down to the LSb. It starts with Qn, Qn−1, …, Q0 = 0b00…0. It then iterates through this algorithm for all bits m in n > m ≥ 0.
• Assume bit m is high, so the value is QnQn−1…Qm+110…0.
• Check the output from the comparator.
• If this guess is ≤ vs(t), keep bit m high. Otherwise, flip bit m back to low.
• Repeat the process for bit m − 1. 11

Figure 8: Visual representation of SAR conver- sion process. First the signal is sampled for a time tS until the sample voltage is within error of the signal. Then the signal is cut out of the circuit, so any changes in the signal do not affect the remaining part of the conversion. A binary
0b1000 search is initiated to find the signal. This search
0t tS tconv
An example of this search for a 4-bit successive approximation ADC is shown in Table 1. Starting with the MSb, each bit is successively tested (shown in red). If the resulting voltage exceeds the analog signal, that bit is cleared back to 0, otherwise it is retained as 1.
• The successive approximation ADC will always take n itera- tions for n-bit conversion, regardless of the magnitude of the input signal.
Successive approximation ADCs are quite common, as the constant conversion time makes it easier to synchronize analog signal pro- cessingwithotherprocessesinthemicrocontroller.
Guess Voltage Result
Signal vs(t)
Sampled voltage vADC Digitized voltage vSAR
always takes n iterations for a n-bit conversion. The entire process takes a time tconv .
2.5 V 3.75 V 3.125 V 3.3475 V
vA < vs vA > vs vA < vs vA > vs
Table 1: Example of using a binary search to find the 4-bit binary equivalent of vs = 3.33 V when Vref =5VThefinalresultis0b1010.

Sampling Errors and Sampling Frequency
What is the error between the true analog signal and the digital conversion?
• At best, the maximum error is half the voltage resolution:
∆vs =±∆V =±Vref 2 2n+1
• This occurs when the digitized signal is a true representation of the analog signal.
Unfortunately, when the analog signal is unknown, the error can be considerably larger. This is because for any given sine wave, there are other sine waves with higher frequencies that provides the same digital signal when sampled at the same fixed interval.
Definition: The Nyquist frequency fS is twice the highest frequency com- ponent of the signal.
fS = 2fmax
As long as a signal is sampled at the Nyquist frequency or higher, the resulting digitized signal is a true representation of the analog signal. This is the Nyquist- Theorem, visual- ized in Figure 10.
Analog Signal
Sampled Signal
Digital Signal
Figure 9: The error is the difference between the true analog signal and the digital signal. Depending on how the sampling time aligns with the signal, the error falls within ± half the voltage resolution.

The Nyquist frequency required for sampling is a major factor in deciding which type of ADC to use. Obviously a microcontroller- driven ADC cannot sample faster than the clock speed of the CPU, but most ADC cannot operate anywhere near that fast.
• Sigma-Delta (Σ − ∆) ADC is a very popular piece of hardware for microcontrollers. These have an error-correction loop, and are very accurate. 6 They also tend to be relatively slow, often slower than 10 kHz. The trade-off is that they are high resolution (even up to 24 bits).
• SAR ADC, as discussed here, is the other main type of ADC used in microcontrollers. These tend to be faster, operating in the 100 kHz to 1 MHz range. The trade-off is that they are lower resolution.
• Flash ADC is the fastest, and can operate up to the clock speed of the microcontroller, so often approximately 1 GHz. These are very specialized circuits, and require 2n stages for a n-bit conversion. Consequently they are probitively expensive and power-hungry even at 8 bits. 7
6 They are based on dual-slope integrating ADCs, you can read the optional sections at the end of this note if you are interested.
Figure 10: Visualization of the Nyquist- Theorem. The sampled data (dots) match all three different sine waves — without further information there is no way to tell which of these is the true signal.
7 You can read the optional section at the end of this note if you are interested in this kind of ADC.

• Finally, pipeline ADC combines a low-resolution flash ADC to subdivide the signal, then a conventional SAR ADC stage refines the conversion to an acceptable resolution. By passing the signal through a coarse and fast flash ADC stage, the SAR ADC requires fewer steps in the binary search to converge to the correct value. This trade-off allows the device to operate around 100 MHz while still having 12 or 16 bits of resolution.

ADC on the DE1-SoC
The DE1-SoC development board has an ADC peripheral. This is an 8-channel, 12-bit ADC which uses the successive-approximation method. 8
• The ADC is memory mapped to the base address 0xff204000.
• The data register for each of the eight channels is mapped to a
sequential word, starting with the base address for channel 0.
• As the ADC is 12-bit, only the 12 LSbs for each register are used for data.
• The register for channel 0 does double duty: it also acts as a control register for the ADC. Writing a value — any value — to this register will cause all channels to update. This means all channels will start converting whatever input is present to a digital value.
• The register for channel 1 also does double duty: it also acts as a control register for the ADC. Writing a 1 to this register will cause all channels to auto-update.
• For all channels, bit 15 is used as a “status bit” to indicate when the conversion is complete. This bit gets set to 1 when the conversion for that channel is complete, and it gets cleared to 0 after that channel is read by the CPU.
The structure of the ADC is shown schematically in Figure 11. 16
8 The peripheral is a commercially-available LTC2308 IC, if you want full technical details of the ADC look up the datasheet for that chip. (Just Googling “LTC2308” should find it.)

31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x1c:Channel7
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x18:Channel6
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x14:Channel5
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x10:Channel4
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x0c:Channel3
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x08:Channel2
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x04:Channel1
31 ··· 1716151413121110 9 8 7 6 5 4 3 2 1 0 [base] + 0x00:Channel0 Auto-Update
Figure 11: Structure of the LTC2308 ADC chip on the DE1-SoC board. The base address is 0x0xff204000. The registers for channels 0 and 1 do double duty as data and control registers. Bit 15 for all channels acts as a “status bit”, informing whether the conversion is complete for that channel.

Interacting with the ADC peripheral in Assembly or C is similar
to using the interval timers: write the contents of whatever register is handy to channel 0 or 1 to set the operating mode, then use ldr with the appropriate address to read from whichever channel is set up.
Example: If we want to read a single value from channels 0 and 3, the following assembly code will do the trick.
ldr r0, =0xff204000 @ ADC base
str r1, [r0] @ write to ch0 to update ADC /* do some things */
ldr r1, [r0] @ read ch0
ldr r1, [r0,#12] @ read ch3
Example: To read a single value from channels 0 and 3, the following C code will do the trick.
#define ADR_BASE 0xFF204000 int ch0, ch3;
// write junk to update ADC
*(unsigned int*)(ADR_BASE) = 1;
// do some things
ch0 = *( unsigned int *)( ADR_BASE );
ch3 = *(unsigned int*)(ADR_BASE + 0xC);

Example: The following Assembly code reads a continuous stream of data from channel 4 and stores it to memory.
ldr r0, ldr r1,
mov r4, str r4,
lsl r4, adc_loop:
=0xff204000 @ ADC base adr_array_base @ where to store data
[r0,#4] @ set ADC to auto-update
#15 @ bit mask for bit 15
[r0,#16] @ read ch4
r2, r4 @ check bit 15 r4
bne adc_loop @ conversion not done yet
sub r2, r4 @ remove bit 15 from data str r2, [r1], #4 @ save data to memory
/* some other code to decide when enough data has been read */
b adc_loop
Example: The following C code reads a continuous stream of data from channel 4 and stores it to memory. Here I create a structure for the ADC, although it isn’t particularly useful in this simple

example. I also only read in 100 data values, instead of an endless amount — actually reading in an endless amount of data is a good way to crash a microcontroller.
// structure for ADC
// this could also be an array since all // channels are basically the same typedef struct _ADC
unsigned int ch0; unsigned int ch1; unsigned int ch2; unsigned int ch3; unsigned int ch4; unsigned int ch5; unsigned int ch6; unsigned int ch7;
volatile ADC* const adc_ptr = (ADC*)ADC_BASE;
// probably should have some idea how many // numbers we will read in
int my_data[100];
// counter for 100 values
// get bit mask
int bit_mask = 1<<15; // value to hold channel data int adc_dat 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com