Virtual Memory III CSE 351 Autumn 2016
Address Translation: Page Hit
1
1) Processor sends virtual address to MMU (memory management unit)
2-3) MMU fetches PTE from page table in cache/memory
(Uses PTBR to find beginning of page table for current process)
4) MMU sends physical address to cache/memory requesting data
5) Cache/memory sends data to processor
MMU
Cache/
Memory
PA
Data
CPU
VA
CPU Chip
PTEA
PTE
1
2
3
4
5
VA = Virtual Address PTEA = Page Table Entry Address PTE= Page Table Entry
PA = Physical Address Data = Contents of memory stored at VA originally requested by CPU
CMPT 295
L21 Virtual Memory
1
Address Translation: Page Fault
2
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in cache/memory
4) Valid bit is zero, so MMU triggers page fault exception
5) Handler identifies victim (and, if dirty, pages it out to disk)
6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restarting faulting instruction
MMU
Cache/
Memory
CPU
VA
CPU Chip
PTEA
PTE
1
2
3
4
5
Disk
Page fault handler
Victim page
New page
Exception
6
7
CMPT 295
L21 Virtual Memory
2
Hmm… Translation Sounds Slow
The MMU accesses memory twice: once to get the PTE for translation, and then again for the actual memory request
The PTEs may be cached in L1 like any other memory word
But they may be evicted by other data references
And a hit in the L1 cache still requires 1-3 cycles
What can we do to make this faster?
Solution: add another cache! 🎉
3
CMPT 295
L21 Virtual Memory
Speeding up Translation with a TLB
Translation Lookaside Buffer (TLB):
Small hardware cache in MMU
Split VPN into TLB Tag and TLB Index based on # of sets in TLB
Maps virtual page numbers to physical page numbers
Stores page table entries for a small number of pages
Modern Intel processors have 128 or 256 entries in TLB
Much faster than a page table lookup in cache/memory
4
Virtual Page Number
Page offset
TLBT
TLBI
TLB
PTE
TLBT
PTE
PTE
PTE
Set
0
1
V
TLBT
V
TLBT
V
V
TLBT
CMPT 295
L21 Virtual Memory
“The architecture of the IBM System/370” R.P. Case and A. Padegs Communications of the ACM. 21:1, 73-96, January 1978.
Perhaps the first paper to use the term translation lookaside buffer. The name arises from the historical name for a cache, which was a lookaside buffer as called by those developing the Atlas system at the University of Manchester; a cache of address translations thus became a translation lookaside buffer. Even though the term lookaside buffer fell out of favor, TLB seems to have stuck, for whatever reason.
“x86info -c” on Intel Core2 Duo CPU:
L1 Data TLB: 4KB pages, 4-way set associative, 16 entries
Data TLB: 4K pages, 4-way associative, 256 entries.
L1 Data TLB: 4MB pages, 4-way set associative, 16 entries
Data TLB: 4MB pages, 4-way associative, 32 entries
4
TLB Hit
A TLB hit eliminates a memory access!
5
MMU
Cache/
Memory
PA
Data
CPU
VA
CPU Chip
PTE
1
2
4
5
TLB
VPN
3
TLB
PTE
VPN
→
PTE
VPN
→
PTE
VPN
→
CMPT 295
L21 Virtual Memory
5
TLB Miss
A TLB miss incurs an additional memory access (the PTE)
Fortunately, TLB misses are rare
6
MMU
Cache/
Memory
PA
Data
CPU
VA
CPU Chip
PTE
1
2
5
6
TLB
VPN
4
PTEA
3
TLB
PTE
VPN
→
PTE
VPN
→
PTE
VPN
→
CMPT 295
L21 Virtual Memory
Does a TLB miss require disk access?
6
Fetching Data on a Memory Read
Check TLB
Input: VPN, Output: PPN
TLB Hit: Fetch translation, return PPN
TLB Miss: Check page table (in memory)
Page Table Hit: Load page table entry into TLB
Page Fault: Fetch page from disk to memory, update
corresponding page table entry, then load entry into TLB
Check cache
Input: physical address, Output: data
Cache Hit: Return data value to processor
Cache Miss: Fetch data value from memory, store it in cache, return it to processor
7
CMPT 295
L21 Virtual Memory
7
Address Translation
8
Virtual Address
TLB Lookup
Check the
Page Table
Update
TLB
Page Fault
(OS loads page)
Protection
Check
Physical
Address
TLB Miss
TLB Hit
Page not
in Mem
Access
Denied
Access
Permitted
Protection
Fault
SIGSEGV
Page
in Mem
Check cache
Find in Disk
Find in Mem
Hit
Miss
CMPT 295
L21 Virtual Memory
CS252 S05
8
Need to restart instruction.
Soft and hard page faults.
Address Manipulation
9
Page offset
Page Offset
Virtual Page Number
TLB Index
request from CPU:
-bit physical address:
split to access TLB:
(on TLB miss) access PT:
-bit virtual address
Page offset
Physical Page Number
Offset
Cache Index
TLB Tag
Cache Tag
split to access cache:
TRANSLATION
CMPT 295
L21 Virtual Memory
CS252 S05
9
Need to restart instruction.
Soft and hard page faults.
Summary of Address Translation Symbols
Basic Parameters
Number of addresses in virtual address space
Number of addresses in physical address space
Page size (bytes)
Components of the virtual address (VA)
VPO Virtual page offset
VPN Virtual page number
TLBI TLB index
TLBT TLB tag
Components of the physical address (PA)
PPO Physical page offset (same as VPO)
PPN Physical page number
10
CMPT 295
L21 Virtual Memory
10
CPU
Page Table Address Translation
11
Virtual page number (VPN)
Virtual page offset (VPO)
Physical page number (PPN)
Physical page offset (PPO)
Virtual address (VA)
Physical address (PA)
Valid
PPN
Page table
base register
(PTBR)
Page table
Page table address
for process
Valid bit = 0:
page not in memory
(page fault)
In most cases, the MMU can perform this translation without software assistance
CMPT 295
L21 Virtual Memory
PTBR is another name for control register 3 (CR3) in x86: http://en.wikipedia.org/wiki/Control_register#CR3
11
Peer Question
How many bits wide are the following fields?
16 KiB pages
48-bit virtual addresses
16 GiB physical memory
12
34 24
(A)
32 18
(B)
30 20
(C)
34 20
(D)
VPN PPN
CMPT 295
L21 Virtual Memory
12
Page Hit
Page hit: VM reference is in physical memory
13
Page Table (DRAM)
null
null
0
1
0
0
1
1
0
1
Valid
PPN/Disk Addr
PTE 0
PTE 7
…
…
Virtual address
Example: Page size = 4 KiB
0x00740b
Virtual Addr:
VPN:
PPN:
Physical Addr:
Physical memory
(DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Virtual memory
(DRAM/disk)
VP 1
VP 2
VP 4
VP 6
VP 7
VP 3
CMPT 295
L21 Virtual Memory
4kB page = 2^12
3 hex digits
13
Page Fault
Page fault: VM reference is NOT in physical memory
14
Page Table (DRAM)
null
null
0
1
0
0
1
1
0
1
Valid
PPN/Disk Addr
PTE 0
PTE 7
…
…
Physical memory
(DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Virtual memory
(DRAM/disk)
VP 1
VP 2
VP 4
VP 6
VP 7
VP 3
Virtual address
Example: Page size = 4 KiB
Provide a virtual address request (in hex) that results in this particular page fault:
Virtual Addr:
CMPT 295
L21 Virtual Memory
14
Simple Memory System Example (small)
Addressing
14-bit virtual addresses
12-bit physical address
Page size = 64 bytes
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VPO
VPN
Virtual Page Number
Virtual Page Offset
11
10
9
8
7
6
5
4
3
2
1
0
PPO
PPN
Physical Page Number
Physical Page Offset
CMPT 295
L21 Virtual Memory
Simple Memory System: Page Table
Only showing first 16 entries (out of _____)
Note: showing 2 hex digits for PPN even though only 6 bits
Note: other management bits not shown, but part of PTE
16
VPN PPN Valid
0 28 1
1 – 0
2 33 1
3 02 1
4 – 0
5 16 1
6 – 0
7 – 0
VPN PPN Valid
8 13 1
9 17 1
A 09 1
B – 0
C – 0
D 2D 1
E – 0
F 0D 1
CMPT 295
L21 Virtual Memory
Size of page table = 2^(n-p) entries
16
Simple Memory System: TLB
16 entries total
4-way set associative
17
13
12
11
10
9
8
7
6
5
4
3
2
1
0
virtual page offset
virtual page number
TLB index
TLB tag
0
–
02
1
34
0A
1
0D
03
0
–
07
3
0
–
03
0
–
06
0
–
08
0
–
02
2
0
–
0A
0
–
04
0
–
02
1
2D
03
1
1
02
07
0
–
00
1
0D
09
0
–
03
0
Valid
PPN
Tag
Valid
PPN
Tag
Valid
PPN
Tag
Valid
PPN
Tag
Set
Why does the TLB ignore the page offset?
CMPT 295
L21 Virtual Memory
Calculate VPN for valid TLB entry using Tag & Set
17
Simple Memory System: Cache
Direct-mapped with = 4 B, = 16
Physically addressed
18
11
10
9
8
7
6
5
4
3
2
1
0
physical page offset
physical page number
cache offset
cache index
cache tag
Note: It is just coincidence that the PPN is the same width as the cache Tag
Index Tag Valid B0 B1 B2 B3
0 19 1 99 11 23 11
1 15 0 – – – –
2 1B 1 00 02 04 08
3 36 0 – – – –
4 32 1 43 6D 8F 09
5 0D 1 36 72 F0 1D
6 31 0 – – – –
7 16 1 11 C2 DF 03
Index Tag Valid B0 B1 B2 B3
8 24 1 3A 00 51 89
9 2D 0 – – – –
A 2D 1 93 15 DA 3B
B 0B 0 – – – –
C 12 0 – – – –
D 16 1 04 96 34 15
E 13 1 83 77 1B D3
F 14 0 – – – –
CMPT 295
L21 Virtual Memory
18
Current State of Memory System
Cache:
TLB:
Page table (partial):
Index Tag V B0 B1 B2 B3
0 19 1 99 11 23 11
1 15 0 – – – –
2 1B 1 00 02 04 08
3 36 0 – – – –
4 32 1 43 6D 8F 09
5 0D 1 36 72 F0 1D
6 31 0 – – – –
7 16 1 11 C2 DF 03
Index Tag V B0 B1 B2 B3
8 24 1 3A 00 51 89
9 2D 0 – – – –
A 2D 1 93 15 DA 3B
B 0B 0 – – – –
C 12 0 – – – –
D 16 1 04 96 34 15
E 13 1 83 77 1B D3
F 14 0 – – – –
Set Tag PPN V Tag PPN V Tag PPN V Tag PPN V
0 03 – 0 09 0D 1 00 – 0 07 02 1
1 03 2D 1 02 – 0 04 – 0 0A – 0
2 02 – 0 08 – 0 06 – 0 03 – 0
3 07 – 0 03 0D 1 0A 34 1 02 – 0
VPN PPN V
0 28 1
1 – 0
2 33 1
3 02 1
4 – 0
5 16 1
6 – 0
7 – 0
VPN PPN V
8 13 1
9 17 1
A 09 1
B – 0
C – 0
D 2D 1
E – 0
F 0D 1
CMPT 295
L21 Virtual Memory
TLB and Cache are separate pieces of hardware; page table stored in memory
Show correlation between TLB & page table (VPN 0x0D and 0x0F in particular)
19
Memory Request Example #1
Virtual Address: 0x03D4
Physical Address:
20
TLBI
TLBT
0
13
0
12
0
11
0
10
1
9
1
8
1
7
1
6
0
5
1
4
0
3
1
2
0
1
0
0
VPO
VPN
11
10
9
8
7
6
5
4
3
2
1
0
PPO
PPN
CO
CI
CT
VPN ______ TLBT _____ TLBI _____ TLB Hit? ___ Page Fault? ___ PPN _____
CT ______ CI _____ CO _____ Cache Hit? ___ Data (byte) _______
Note: It is just coincidence that the PPN is the same width as the cache Tag
CMPT 295
L21 Virtual Memory
TLB Hit, Cache Hit
20
Memory Overview
21
Disk
Main memory
(DRAM)
Cache
CPU
Page
Page
Line
Block
requested 32-bits
LD t1, 0 (sp)
TLB
MMU
CMPT 295
L21 Virtual Memory
Practice VM Question
Our system has the following properties
1 MiB of physical address space
4 GiB of virtual address space
32 KiB page size
4-entry fully associative TLB with LRU replacement
Fill in the following blanks:
22
________ Entries in a page table ________ Minimum bit-width of PTBR
________ TLBT bits ________ Max # of valid entries in a page table
CMPT 295
L21 Virtual Memory
Practice VM Question
One process uses a page-aligned square matrix mat[] of 32-bit integers in the code shown below:
#define MAT_SIZE = 2048
for(int i = 0; i < MAT_SIZE; i++)
mat[i*(MAT_SIZE+1)] = i;
What is the largest stride (in bytes) between successive memory accesses (in the VA space)?
23
CMPT 295
L21 Virtual Memory
23
Practice VM Question
One process uses a page-aligned square matrix mat[] of 32-bit integers in the code shown below:
#define MAT_SIZE = 2048
for(int i = 0; i < MAT_SIZE; i++)
mat[i*(MAT_SIZE+1)] = i;
Assuming all of mat[] starts on disk, what are the following hit rates for the execution of the for-loop?
24
________ TLB Hit Rate ________ Page Table Hit Rate
CMPT 295
L21 Virtual Memory
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