CS计算机代考程序代写 RISC-V RISC-V Instruction Set Core Instruction Formats

RISC-V Instruction Set Core Instruction Formats
31 27 26 25 24 20 19
RV32I Base Integer Instructions
Inst
add
sub
xor
or
and
sll
srl
sra
slt
sltu
addi
xori
ori
andi
slli
srli
srai
slti
sltiu
lb
lh
lw
lbu
lhu
sb
sh
sw
beq
bne
blt
bge
bltu
bgeu
jal
jalr
lui
auipc
ecall
ebreak
15 14 12 11
7
6
0
RISC-V Reference
CMPT 295 Relevant Instructions
funct7
rs2
rs1
funct3
rd
opcode
imm[11:0]
rs1
funct3
rd
opcode
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
imm[12|10:5]
rs2
rs1
funct3
imm[4:1|11]
opcode
imm[31:12]
rd
opcode
imm[20|10:1|11|19:12]
rd
opcode
R-type I-type S-type B-type U-type J-type
Name
FMT
Opcode
funct3
funct7
Description (C)
ADD
SUB
XOR
OR
AND
Shift Left Logical Shift Right Logical Shift Right Arith* Set Less Than
Set Less Than (U)
R R R R R R R R R R
0110011
0110011
0110011
0110011
0110011
0110011
0110011
0110011
0110011
0110011
0x0
0x0
0x4
0x6
0x7
0x1
0x5
0x5
0x2
0x3
0x00
0x20
0x00
0x00
0x00
0x00
0x00
0x20
0x00
0x00
rd = rs1 + rs2
rd = rs1 – rs2
rd = rs1 ˆ rs2
rd = rs1 | rs2
rd = rs1 & rs2
rd = rs1 << rs2 rd = rs1 >> rs2
rd = rs1 >> rs2
rd = (rs1 < rs2)?1:0 rd = (rs1 < rs2)?1:0 ADD Immediate XOR Immediate OR Immediate AND Immediate Shift Left Logical Imm Shift Right Logical Imm Shift Right Arith Imm Set Less Than Imm Set Less Than Imm (U) I I I I I I I I I 0010011 0010011 0010011 0010011 0010011 0010011 0010011 0010011 0010011 0x0 0x4 0x6 0x7 0x1 0x5 0x5 0x2 0x3 imm[5:11]=0x00 imm[5:11]=0x00 imm[5:11]=0x20 rd = rs1 + imm rd = rs1 ˆ imm rd = rs1 | imm rd = rs1 & imm rd = rs1 << imm[0:4] rd = rs1 >> imm[0:4]
rd = rs1 >> imm[0:4]
rd = (rs1 < imm)?1:0 rd = (rs1 < imm)?1:0 Load Byte Load Half Load Word Load Byte (U) Load Half (U) I I I I I 0000011 0000011 0000011 0000011 0000011 0x0 0x1 0x2 0x4 0x5 rd = M[rs1+imm][0:7] rd = M[rs1+imm][0:15] rd = M[rs1+imm][0:31] rd = M[rs1+imm][0:7] rd = M[rs1+imm][0:15] Store Byte Store Half Store Word S S S 0100011 0100011 0100011 0x0 0x1 0x2 M[rs1+imm][0:7] = rs2[0:7] M[rs1+imm][0:15] = rs2[0:15] M[rs1+imm][0:31] = rs2[0:31] Branch == Branch != Branch < Branch ≤ Branch < (U) Branch ≥ (U) B B B B B B 1100011 1100011 1100011 1100011 1100011 1100011 0x0 0x1 0x4 0x5 0x6 0x7 if(rs1 == rs2) PC += imm if(rs1 != rs2) PC += imm if(rs1 < rs2) PC += imm if(rs1 >= rs2) PC += imm
if(rs1 < rs2) PC += imm if(rs1 >= rs2) PC += imm
Jump And Link Jump And Link Reg
J I
1101111
1100111
0x0
rd = PC+4; PC += imm
rd = PC+4; PC = rs1 + imm
Load Upper Imm
Add Upper Imm to PC
U U
0110111
0010111
rd = imm << 12 rd = PC + (imm << 12) Environment Call I 1110011 0x0 imm=0x0 Transfer control to OS Environment Break I 1110011 0x0 imm=0x1 Transfer control to debugger Note msb-extends zero-extends msb-extends zero-extends zero-extends zero-extends zero-extends zero-extends 1 RISC-V Reference Card V0.1 Standard Extensions RV32M Multiply Extension Inst mul mulh mulsu mulu div divu rem remu RV32A Atomic Extension Not Relevant for CMPT-295 Name FMT Opcode funct3 funct7 MUL MUL High MUL High (S) (U) MUL High (U) DIV DIV (U) Remainder Remainder (U) R R R R R R R R 0110011 0110011 0110011 0110011 0110011 0110011 0110011 0110011 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 Description (C) rd = (rs1 * rs2)[31:0] rd = (rs1 * rs2)[63:32] rd = (rs1 * rs2)[63:32] rd = (rs1 * rs2)[63:32] rd =rs1/rs2 rd =rs1/rs2 rd =rs1%rs2 rd =rs1%rs2 1211 76 0 31 Inst lr.w sc.w amoswap.w amoadd.w amoand.w amoor.w amoxor.w amomax.w amomin.w RV32F / D Floating-Point Extensions Inst flw fsw fmadd.s fmsub.s fnmadd.s fnmsub.s fadd.s rd=rs1+rs2 fsub.s rd=rs1-rs2 fmul.s rd=rs1*rs2 fdiv.s rd=rs1/rs2 27 26 25 24 20 19 15 14 funct5 aq rl rs2 rs1 funct3 rd opcode 51155357 Name FMT Opcode funct3 funct5 Load Reserved Store Conditional Atomic Swap Atomic ADD Atomic AND Atomic OR Atomix XOR Atomic MAX Atomic MIN R R R R R R R R R 0101111 0101111 0101111 0101111 0101111 0101111 0101111 0101111 0101111 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x02 0x03 0x01 0x00 0x0C 0x0A 0x04 0x14 0x10 fsqrt.s fsgnj.s fsgnjn.s fsgnjx.s fmin.s fmax.s fcvt.s.w fcvt.s.wu rd = (float) rs1 fcvt.w.s fcvt.wu.s rd = (uint32_t) rs1 fmv.x.w fmv.w.x feq.s flt.s fle.s fclass.s rd = *((int*) &rs1) rd = *((float*) &rs1) rd=(rs1==rs2)? 1: 0 rd=(rs1 zero
Copy single-precision register Single-precision absolute value Single-precision negate
Copy double-precision register Double-precision absolute value Double-precision negate
Branch if = zero
Branch if ̸= zero
Branch if ≤ zero
Branch if ≥ zero
Branch if < zero Branch if > zero
Branch if >
Branch if ≤
Branch if >, unsigned
Branch if ≤, unsigned
Jump
Jump and link
Jump register
Jump and link register
Return from subroutine
Call far-away subroutine
Tail call far-away subroutine Fence on all memory and I/O
CMPT 295 Relevant Instructions
Pseudo Instructions
addi rd, rs, 0
xori rd, rs, -1
sub rd, x0, rs
subw rd, x0, rs
addiw rd, rs, 0
sltiu rd, rs, 1
sltu rd, x0, rs
slt rd, rs, x0
slt rd, x0, rs
fsgnj.s rd, rs,
fsgnjx.s rd, rs, rs
fsgnjn.s rd, rs, rs
fsgnj.d rd, rs, rs
fsgnjx.d rd, rs, rs
fsgnjn.d rd, rs, rs
beq rs, x0, offset
bne rs, x0, offset
bge x0, rs, offset
bge rs, x0, offset
blt rs, x0, offset
blt x0, rs, offset
blt rt, rs, offset
bge rt, rs, offset
bltu rt, rs, offset
bgeu rt, rs, offset
jal x0, offset
jal x1, offset
jalr x0, rs, 0
jalr x1, rs, 0
jalr x0, x1, 0
auipc x1, offset[31:12]
jalr x1, x1, offset[11:0]
auipc x6, offset[31:12]
jalr x0, x6, offset[11:0]
fence iorw, iorw
rs
bgtu rs,
bleu rs,
j offset
jal offset
jr rs
rt, offset
rt, offset
jalr rs ret
call offset
tail offset
fence
4

RISC-V Reference Card
V0.1
Registers
Register
x0
x1
x2
x3
x4
x5
x8
x9
x10-x11
x12-x17
x18-x27
x28-x31
f0-7
f8-9
f10-11
f12-17
f18-27
f28-31
Saver — Caller —
— Callee Caller Callee Callee Caller Caller Callee Caller Caller Callee Caller Caller Callee Caller
CMPT 295 Relevant
ABI Name
Description
zero
ra
sp
gp
tp
t0-t2
s0 / fp
s1
a0-a1
a2-a7
s2-s11
t3-t6
Zero constant
Return address
Stack pointer
Global pointer Thread pointer Temporaries
Saved / frame pointer Saved register
Fn args/return values Fn args
Saved registers Temporaries
ft0-7
fs0-1
fa0-1
fa2-7
fs2-11
ft8-11
FP temporaries
FP saved registers
FP args/return values FP args
FP saved registers
FP temporaries
5