CS计算机代考程序代写 On wave diagrams

On wave diagrams

On wave diagrams
Y=A OR B
What will be the waveform of output Y (Class Poll)

Sequential Circuits and Memory

Combinational vs. Sequential
■ Combinational circuit
◆ Always gives the same output for a given set of
■ Sequential circuit
◆ Remembers previous input
◆ Output depends on state and input
inputs
◆ Example: Adder always generates sum and carry, regardless of previous inputs

Sequential Circuits
■ Store information
■ Output depends on stored information (state) plus
input
◆ So a given input might produce different outputs, depending on the stored information
■ Example: ticket counter
◆ Advances when you push the button ◆ Output depends on previous state

State Machine
The basic type of sequential circuit
◆ Combines combinational logic with storage
◆ “Remembers” state, and changes output (and state) based on inputs and current state
State Machine
Combinational Logic Circuit
Storage Elements
Inputs Outputs

Example of State Machine: Traffic Light

State Machine: Overview

State Machine: Traffic Light
Red State
Transition Logic:
If Xs change
else remain
Green State
Yellow State
Transition Logic:
If Ys change
else remain
Transition Logic:
If Zs change
else remain

State Machine: Traffic Light
Red State
Transition Logic:
If Xs change
else remain
Green State
Yellow State
Transition Logic:
If Ys change
else remain
Transition Logic:
If Zs change
else remain
● StartoffindefaultstateRed

Latch
■ Output is equal to Input when clk is high.
Level sensitive
Stores last value when clk is low.
■ ■

Latch
■ ■
Output is equal to Input when clk is high. Stores last value when clk is low.

D Flip-Flops
Memory device
Can be positive edge triggered or negative
edge triggered (by a clock usually abbreviated
by clk)
■
■ ■
◆ D: input signal
◆ clk: Clock signal
◆ en:if0Qholdsitsvalue,if1,Q
Different types e.g. RS, JK Inputs/Outputs:
becomes D at clk edge.
◆ rst: if 1 then Q becomes 0
◆ Q: output signal

D flip-flop(positive-edge) timing diagram
■ Q becomes D at positive clk edge (0 -> 1). ◆ Stores value until next positive clk edge.
■ clk oscillates between 0 and 1 ◆ frequency=1/period

D flip-flop(positive-edge) timing diagram
■ Q becomes D at positive clk edge.
◆ Stores value until next positive clk edge.
■ clk oscillates between 0 and 1 ◆ frequency=1/period

D flip-flop(negative-edge) timing diagram
■ Q becomes D at negative clk edge.
◆ Stores value until next negative clk edge.
■ clk oscillates between 0 and 1 ◆ frequency=1/period

Setup and Hold Time
Setup time: Time before clock edge where signal has to be stable
Hold time: Time after clock edge where signal has to be stable
■
■

One way to make a Flip-Flop: Two Latches
One latch(master) is connected to clk’ and the other(slave) to clk (positive triggered).
When clk transitions to high, slave captures last value of master which is now stored since it’s clk is low.
■
■

One way to make a Flip-Flop: Two Latches
When clk transitions to high, slave captures last value of master which is now stored since it’s clk is low.
When clk transitions to low Master is open again but slave is closed, retaining value
■
■

Reset-Set (RS) Latch – or SR
■ Two inputs: Set and Reset
■ Setto0oneofthetwoinputsatatimetostore
a value, S sets, R clears
■ The transition to 00 generates an undefined output

R-S Latch

R-S Latch Nor Gates

Four SR Latch States: S’ 0, R’ 0
0
0
1
1

Four SR Latch States: S’ 0, R’ 1
0
1
1
1
0

Four SR Latch States: S’ 1, R’ 0
1
1
0
0
1

Four SR Latch States: S’ 1, R’ 1 Memory
1
1
Q = 1, Q’ = 0
1
0

Four SR Latch States: S’ 1, R’ 1 Memory
1
0 1
1
Q = 1, Q’ = 0
1
0

Four SR Latch States: S’ 1, R’ 1 Memory
1
1
Q = 0, Q’ = 1
0
1

Four SR Latch States: S’ 1, R’ 1 Memory
1
1 0
1
Q = 0, Q’ = 1
0
1

D Latch
S’
R’
E/clk D R’ 0 0 1
S’ Q Q’ Comment 1 Q Q’ Keepstate

D Latch
S’
R’
E/clk D R’ 0 0 1 0 1 1
S’ Q Q’ Comment 1 Q Q’ Keepstate 1 Q Q’ Keepstate

D Latch
1
0
R’
1 S’
E/clk D R’ 0 0 1 0 1 1
S’ Q Q’
1 Q Q’ Keepstate 1 Q Q’ Keepstate
Comment
1
0
0101D=Q

D Latch
0
1
R’
0 S’
E/clk D R’ 0 0 1 0 1 1
S’ Q Q’
1 Q Q’ Keepstate 1 Q Q’ Keepstate
Comment
1 1
0 1
011D=Q 100D=Q
0 1

Other types of memory…
SRAM DRAM
(on-chip usually) (off-chip usually)
NAND FLASH
(on or off-chip, non-volatile)

Memory
Now that we know how to store bits,
we can build a memory – a logical k × m array of stored bits.
• • •
Address Space:
number of locations (usually a power of 2)
Addressability:
number of bits per location (e.g., byte-addressable)
k = 2n locations
m bits

22 x 3 Memory
word select
input bits
address
write enable
address decode
r
output bits
word WE

Let’s Build a Computer

Basic Computer
Memory
Execute
Control
Memory: Could be Flip Flops, SRAM/DRAM, Flash etc
Execute: Combinational Logic (Adder, Shifter, Rotation etc)
Control: Finite State Machine (combination of sequential and combinational logic circuits)

Data Path
Combinational Logic
Storage
State Machine

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