Von Neumann and MIPS
References:
1) MIPS_Vol2.pdf
2) Intro to MIPS Assembly Language Programming
Von Neumann Architecture
CPU
Memory
Address Data
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Harvard Architecture
Instruction Address
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Inst. Data Data Address
CPU
Instruction Memory
Data Memory
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Advantages/Disadvantages
■ Advantages
◆ Harvard can have different memory sizes
◆ Harvard can access both memories at the same time
◆ Harvard can have different types of memory ★ Flash for program
★ SRAM for data
◆ Instructions can be read-only
■ Disadvantages
◆ Can run out of one but not the other ◆ Requires two memories
◆ No self modifying programs? CSE 12 Fall 2020
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Modified Harvard Architecture
Instruction Address
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Data
Address Data
CPU
Inst.
Data Address
Instruction Cache
Data Cache
MUX
Memory
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Notations
■ Sets of Bits
◆ A[3:0]denotesasetof4bits:A ,A ,A ,A
3210
◆ The content of an n-bit register R is referred to as R[n-1:0]
★ Rn-1 is the most significant bit (MSB), or leftmost bit
★ R0istheleastsignificantbit(LSB),orrightmostbit
★ Given R[31:0], R[7:4] refers to the four bits from R7 down to R4
■ Bit Assignment
◆ R2[5:0]⇐R1[13:8]
★ Meansthatbits5to0ofregisterR2getassignedthevaluesofbits13to8ofregisterR1. ■ Contents
★ (Reg1)means“contentofReg1”
★ Mem[loc]means“contentofmemorylocationloc”(i.e.,locistheaddress) ★ [Reg1]meansthe“contentsofmemoryataddressinReg1”
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Registers
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MIPS Registers
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Register File (2)
9
■ Temporary can be used $t0…$t9 ◆ Procedures can modify these
■ Saved can be used $s0..$s7, but are caller save ◆ Procedures must save/restore these
■ $zero (or $0) is always 0
■ $a0..a3 Are passed to functions as parameters
■ $v0..v1 Are returned from functions
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MIPS Memory
■ 32-bit “flat” memory model
◆ Address 0x00000000 to 0xFFFFFFFF ◆ How much memory is that?
◆ What if I want less?
◆ What if I want more?
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Memory “Segments”
■ Three segments for now
◆ Reserved:
★ 0x0000_0000 to 0x0040_0000 ★ Special code for I/O and OS
★ 0x0040_0000 to 0x1000_0000
◆ Program Text:
★ Machine code for your instructions!
◆ StaticData
★ 0x1001_0000 to 0x1004_0000
★ Data that is allocated before your program runs
■ What is a segmentation fault? CSE 12 Fall 2020
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MIPS Data Path (much more later!)
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MIPS Example
Not Divisible By Four Program ■ Sequence of 5 Instructions
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Memory Unit
■ Instructionsstoredinmemory.
■ Thefirstinstructionisalwaysat0x00400000
■ Eachinstructionis32bitslong(4Bytes,1byte=8bits) ■ 5instructions=5*4bytes=20bytes(sizeofthe
program).
■ Instructionsstoredsequentiallyinmemorywiththe
address of the next instruction being +4 of the previous instruction
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Instruction in Binary
548
■ addi$t1,$0, -0x20090224
0010 0000 0000 1001 0000 0010 0010 0100
■ addiisanI-Typeinstruction(immediate-type) ◆ op rt, rs, imm:
★ rt- ,rs-source1,imm-immediate
op – 6 bits
rs –
rs –
5 bits
5 bits
rt – 5 bits
rt – 5 bits
imm – 16 bits
imm – 16 bits
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op – 6 bits
destination
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Instruction in Binary
548
■ addi$t1,$0, -0x20090224
0010 0000 0000 1001 0000 0010 0010 0100
■ addiisanI-Typeinstruction(immediate-type) ◆ op rt, rs, imm:
★ rt- ,rs-source1,imm-immediate
op – 6 bits
001000
rs –
rs –
5 bits
5 bits
rt – 5 bits
rt – 5 bits
imm – 16 bits
imm – 16 bits
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destination
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Instruction in Binary
0010 00
548
■ addi$t1,$0, -0x20090224
0 1001 0000 0010 0010 0100
■ addiisanI-Typeinstruction(immediate-type) ◆ op rt, rs, imm:
★ rt- ,rs-source1,imm-immediate
op – 6 bits
001000
destination
rs –
00000
5 bits
rt – 5 bits
rt – 5 bits
imm – 16 bits
imm – 16 bits
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00 000
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Instruction in Binary
0010 00
00 000
548
■ addi$t1,$0, -0x20090224
0000 0010 0010 0100
■ addiisanI-Typeinstruction(immediate-type) ◆ op rt, rs, imm:
★ rt- ,rs-source1,imm-immediate
0 1001
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op – 6 bits
001000
destination
rs –
00000
5 bits
rt – 5 bits
01001
imm – 16 bits
imm – 16 bits
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Instruction in Binary
0010 00
548
■ addi$t1,$0, -0x20090224
0000 0010 0010 0100
■ addiisanI-Typeinstruction(immediate-type) ◆ op rt, rs, imm:
★ rt- ,rs-source1,imm-immediate
op – 6 bits
001000
destination
rs –
00000
5 bits
rt – 5 bits
01001
imm – 16 bits
0000 0010 0010 0100
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00 000
0 1001
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rs and rt are Register Addresses
■ addi$t1,$0, -0x20090224
■ addiisanI-Typeinstruction ◆ op rt, rs, imm:
★, ■ rs=$0-register0
■ rt = $t1 – register 9
source,
destination
op – 6 bits
001000
0010 00
00 000
rs – 5 bits
00000
0 1001
0000 0010 0010 0100
rt –
01001
5 bits
imm – 16 bits
0000 0010 0010 0100
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548
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Introduction to MIPS Assembly
References:
1) MIPS_Vol2.pdf
2) Intro to MIPS Assembly Language Programming
MIPS Overview
■
■
■
Different Type of Instructions (so far we know R-type and I-Type, will learn J-type soon) Natively 2’s complement for representing binary numbers (unsigned options available) Different addressing modes (will learn soon):
◆ Immediate (non-memory addressing mode)
◆ Register (non-memory addressing mode)
◆ Direct, Indirect & Base+Offset (memory addressing modes)
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MIPS Instruction Review
I-type instructions: ■ addi$t1,$0,
■ oprs,rt,imm:
◆ rt- ,rs-source1,imm-immediate
R-type instructions: ■ or$v0,$t2,$t4
■ oprs,rt,rd,shiftamount,funct: ★-,-,
op – 6 bits
rs – 5 bits
rt – 5 bits
imm – 16 bits
op – 6 bits
destination
548
rd
destination
rs – 5 bits
rt – 5 bits
rs
source 1
rd – 5 bits
rt source 2
shamt – 5 bits
funct – 6 bits
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MIPS Overview – Commands
MIPS instructions can be broken down into 3 categories:
■ Data Movement
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◆ Move data between memory and registers
★ For example: lw is load word, sw is store word
■ Operate
◆ Manipulate data directly
★ For example: add is addition, xor is logical ■ Control
◆ Change the sequence of instruction execution
★ For example: b is branch, jal is jump and link, ret is return
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MIPS Overview – Commands
MIPS instructions can be broken down into 3 categories:
■ Data Movement
◆ Move data between memory and registers
★ For example: lw is load word, sw is store word
■ Operate
◆ Manipulate data directly
★ For example: add is addition, xor is logical ■ Control
◆ Change the sequence of instruction execution
★ For example: b is branch, jal is jump and link, ret is return
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Operate: R-Type Logical Instructions
■ AND, OR, NOR, XOR
◆ Uses bit-wise logical operation ◆ Example:
★ AND $t1, $t2, $t3 ★ $t1 = $t2 & $t3
• For all 32 bits…
–Bit 0 of $t2 ANDed with bit 0 of $t3 and put in bit 0 of $t1
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Operate: Arithmetic Instructions
■ Arithmetic Signed
◆ Uses 2’s complement integers ◆ Example:
★ ADD $t1, $t2, $t3 ★ $t1 = $t2 + $t3
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Operate: Shift Logical
■ Shift left or right logical
◆ Number of bits to shift is shamt value
■ Example:
◆ SLL $t1, $t2, 4
★ $t1=$t2<<4 ◆ SRL $t1, $t2, 2
★ $t1=$t2>>2
■ Lower bits dropped in SRL
◆ Equivalent to integer divide by 2 for each bit shifted ■ Zeros inserted in SLL or SRL
◆ Equivalent to integer multiply by 2 for each bit shifted CSE 12 Fall 2020
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Operate: Shift Logical Variable
■ Shift left or right logical
◆ Similar behavior to Shift Logical
◆ Except number of bits to shift is in register
■ Example:
◆ SLLV $t1, $t2, $t3 ★ $t1 = $t2 << $t3
◆ SRLV $t1, $t2, $t3 ★ $t1 = $t2 >> $t3
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Operate: Shift Arithmetic (and Variable)
■ Similar to Logical and Logical Variable Shifts ◆ Except right shifts extend the sign bit
■ Examples:
◆ SRA $t1, $t2, 3
★ $t1 = sign_extend($t2 >> 3)
◆ SRAV $t1, $t2, $t3
★ $t1 = sign_extend($t2 >> $t3)
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Set Operations
■ Set on less than
◆ Two registers (SLT and SLTU)
◆ Register and Immediate (SLTI and SLTIU)
◆ Unsigned or Signed (SLT/SLTI vs SLTU/SLTIU)
■ Destination register is 0 or 1 decimal
■ Example:
◆ SLT $t1, $t2, $t3
◆ Sets $t1 to 1 if $t2<$t3 ◆ Otherwise, $t1 is 0
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