CS计算机代考程序代写 assembly CHAPTER 7 – ASSEMBLY LANGUAGE INSTRUCTIONS

CHAPTER 7 – ASSEMBLY LANGUAGE INSTRUCTIONS

CHAPTER 11
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ASSEMBLY LANGUAGE INSTRUCTIONS
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SSK 3207 – Chapter 11

TOPICS

11.1) Introduction
11.2) Data Transfer Instructions
11.3) Arithmetic Instructions
11.4) Bit Shifting Instructions
11.5) Looping Instructions
11.6) Unconditional Transfer Instructions
11.7) Conditional Transfer Instructions
11.8) Other Instructions
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SSK 3207 – Chapter 11

11.1) Introduction
 Symbolic language (assembly language instructions) for Intel processor family can be categorized into:

arithmetic
ASCII-BCD conversion
Bit shifting
comparison
data transfer
flag operation
input/output
logic operation

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looping
processor control
stack operations
string operations
transfer (conditional and unconditional)
type conversion

Note: To know the symbols for each instruction in detail, refer to Chapter 6 (IBM PC Assembly Language and Programming – Peter Abel). This course will only explain a part of the above category.
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11.2) Data Transfer Instructions
There are a few of instructions that categorized as the data transfer instructions, such as LOAD, MOVE, EXCHANGE and TRANSLATE.

 The following are a few examples of data transfer instructions.

MOV Instruction

 MOV is a 2-address instruction.

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[Label :] MOV register/memory , register/memory/immediate

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This instruction will transfer data from the second address field into the first address field.

The content in second address field will remain unchanged.

 Both fields must be of same size (whether both are byte, word or double word).
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Some examples on MOV:

BYTEFLD DB ? ; define byte
WORDFLD DW ? ; define word

MOV EDX , ECX ; register to register
MOV BYTEFLD , DH ; register to memory
MOV WORDFLD , 1234 ; immediate to memory
MOV CH , BYTEFLD ; memory to register
MOV CX , 40H ; immediate to register
MOV AX , DS ; segment register to ; register
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 Move-and-Fill Instructions:
 MOVSX
 MOVZX

For the MOV instruction, source and destination must be in equal size. (eg, byte-to-byte, word-to-word).

For MOVSX and MOVZX instructions facilitate transferring data from a byte or word source to a word or doubleword destination.
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MOVSX
 used with signed arithmetic value.
 moves a byte or word to the destination with size of word or double word and all the leftmost bits of destination will be filled with the sign bit.

MOVZX
 used with unsigned arithmetic value
 moves a byte or word to the destination with size of word or double word and the leftmost bit of destination will be filled with the value 0.
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[Label:] MOVSX/MOVZX register/memory, register/memory/immediate

Examples:

MOVSX CX, 10110000B ; CX = 11111111 10110000
MOVZX CX, 10110000B ; CX = 00000000 10110000

MOVSX AX, 00001010B ; AX = 00000000 00001010
MOVZX AX, 00001010B ; AX = 00000000 00001010
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 XCHG Instruction
This instruction is used to change the value of source into that of the destination and vice versa.

Example:
XCHG CL, BH ; exchange the contents of ; the two register, CL and ; BH.

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SSK 3207 – Chapter 11
[Label :] XCHG register/memory, register/memory

11.3) Arithmetic Instructions

IBM PC has 2 sets of arithmetic instructions, for binary data and for ASCII or BCD data.
This chapter will only discuss a few arithmetic instructions for binary data (Table 10.2).
There are two types of binary data, signed and unsigned.
Most of the examples are for unsigned binary data.
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For unsigned data, all bits are intended to be data bits. For signed data, the leftmost bit is a sign bit.
Table 10.1 below gives the maximum values for unsigned and signed data according to register width

Table 10.1
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FORMAT BYTE WORD DOUBLEWORD
Unsigned 255 65 535 4 294 967 295
Signed 127 32 767 2 147 483 647

Table 10.2
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Instruction Description Instruction Description
ADC Add with carry IDIV Divide signed
ADD Add IMUL Multiply signed
CBW Convert byte to word MUL Multiply unsigned
CDQ Convert doubleword to quadword NEG Negate
CWD Convert word to doubleword SBB Subtract with borrow
CWDE Convert word to extended doubleword SUB Subtract
DIV Divide unsigned

 Addition and Subtraction Instructions
Table 10.3 shows the format for ADD and SUB instructions.
ADD and SUB are 2-address instructions.
The first address field is for 1st operand and result while the second address field is for 2nd operand.

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Table 10.3
SSK 3207 – Chapter 11

The following are example of the ADD and SUB instructions:

BYTE1 DB 24H ;Data elements
WORD1 DW 4000H
. . .
MOV CL , BYTE1 ; byte processing
MOV DL , 40H
ADD CL , DL ; register to register
SUB CL , 20H ; Immediate from register
ADD BYTE1 , BL ; register to memory
MOV CX , WORD1 ; word processing
MOV DX , 2000H
SUB CX , DX ; register from register
SUB CX , 124H ; Immediate from memory
ADD WORD1 , DX ; register to memory
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 Multiplication Instructions
MUL is a multiplication instruction for unsigned data. This instruction affects the Carry and Overflow flag.

Below is the format for MUL instruction.

MUL is a one address instruction, hence it requires an accumulator to hold 1st operand and result.

In IBM PC, the AX register acts as an accumulator.

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[ Label:] MUL Register/memory

There are 3 types of MUL instruction:

 Byte-times-bytes
 word-times-word
 Doubleword-times-doubleword
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Address field in the MUL instruction refer to the multiplier that will determine the size and position of multiplicand and result (product).

Example 1, Example 2 and Example 2 are a few examples of the MUL instructions together with the size and position of multiplier, multiplicand and result (product).

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Table 10.4
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BYTE1 DB 80H
BYTE2 DB 40H
WORD1 DW 8000H
WORD2 DW 2000H
DWORD1 DD 00018402H
DWORD2 DD 00012501H
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Example 3:
MOV AL, BYTE1 ; using the above data ; definition
MUL BYTE2 ; byte times byte, product ; in AX register

 Value 80H (128) is multiplied with 40H (64) and the result 2000H (8,192) is kept in AX register.
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MOV AX, WORD1 ; using the above data ; definition
MUL WORD2 ; word x word, product in ; DX:AX

 Value 8000H is multiplied with 2000H and the result, 1000 0000H is kept in a pair of registers, DX:AX.
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 Divide Instruction
 DIV is a divide instruction for unsigned data. Below is a format for DIV instruction.

Three types of divide operations:

 byte into word
 word into doubleword
 doubleword into quadword.

 As in MUL instruction, address field in the DIV instruction is refer to the divisor (2nd operand) that determines the size and position of dividend, quotient and remainder.
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[label:] DIV Register/memory

 Example 1, Example 2 and Example 3 are a few examples of the DIV instructions together with the size and position of divisor, dividend, quotient and remainder.

Example1 : (using register addressing mode)
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Example 2 : (using direct addressing mode)
– divisor is predefined in the memory

BYTE1 DB ? ; Byte value
WORD1 DW ? ; Word value
DWORD1 DD ? ; Doubleword value
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Example 3:
BYTE1 DB 80H
BYTE2 DB 16H
WORD1 DW 2000H
WORD2 DW 0010H
WORD3 DW 1000H
 MOV AX, WORD1
DIV BYTE1

 In the above example, the value 2000H (8,192) will be divided with 80H (128).
 The quotient (hasil), 40H (64) will be kept in the AL register while its remainder (baki), 00H is in the AH.
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 MOV DX, WORD2
MOV AX, WORD3 ; dividend in DX:AX ; (WORD2:WORD3)
DIV WORD1 ; remainder:quotient ; in DX:AX

 In the above example, the value 00101000H will be divided with 2000H.

 The remainder, 1000H will be kept in the DX register, whereas its result, 0080H will be kept in the AX register.
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11.4) Bit Shifting Instruction
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 Shifting Bits Right
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The instructions are SHR (for unsigned data) and SAR (for signed data).

The format is as follow:

the value of the 2nd address field (Immediate or in CL register) is the shift value that determine how many bits to shift.

the shifted out bit will enter the Carry Flag.

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[label :] SHR/SAR Register/Memory, CL/immediate

Example 1 : (SHR instructions)
the SHR instruction (for unsigned data) will enter the value 0 to the leftmost bit after the shift.
the Carry flag will contain the shifted out bit.

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Example 2: (SAR instruction)
 The SAR instruction (for signed data) will enter the sign bit (0 for +ve data or 1 for –ve data) into the leftmost bit after every shift.
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 the Carry flag will contain the shifted out bit as in SHR instruction.
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 Shifting Bits Left
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The instructions are SHL (for unsigned data) and SAL (for signed data).

The format is as follow:

the value of the 2nd address field (Immediate or in CL register) is the shift value that determine how many bits to shift.

the shifted out bit will enter the Carry Flag.

SSK 3207 – Chapter 11
[label: ] SHL/SAL Register/Memory, CL/immediate

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The shift left instruction is equal to the multiplication operation of the value with

2(number of bit to shift).

1-bit shift to the left is equivalent to the multiplication of a value with 21, a 2-bit shift to the left is equivalent to the multiplication of a value with 4 or 22, and so forth.

 the result of the shift left operation is same for both SHL and SAL.
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Example: (SHL instructions)
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Instructions Comments Binary Decimal CF
MOV BH, 00000101B ; Initialize BH 00000101 5
SHL BH, 01 ; Shift 1-bit to the left 00001010 10 0
MOV CL, 02 ; Set shift value
SHL BH, CL ; Shift 2-bit more to the left 00101000 40 0
SHL BH, CL ; Shift 2-bit more to the left 10100000 160 0

 Rotating Bits Right
This instruction will rotate the bit to the right. Every bit rotated will enter the carry flag.
ROR is for unsigned data whereas RCR is for signed data.
Bit movement is as below:

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 The following is a format for rotating bits right instruction.
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The difference between ROR and RCR is in RCR, every bit that is rotated will enter the carry flag before entering the leftmost bit
Examples: (ROR instruction)
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 ROL/RCL: Rotating Bits Left
ROL/RCL is an operation that will rotate the leftmost bit to the rightmost.
Every bit that is rotated will enter the Carry Flag. ROL is for unsigned data whereas RCL is for signed data. The data movement is depicted as below:

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Example: (ROL instruction)
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11.5) Looping Instructions
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Table below shows the types of looping instructions.

The format for LOOP/LOOPnn is as follow:

These instructions require an initial value in CX register. Before each iteration or loop, the value in CX register will decrease by 1.

SSK 3207 – Chapter 11
Instructions Descriptions Instructions Descriptions
LOOP Loop until Complete LOOPNZ Loop while not Zero
LOOPE Loop while Equal LOOPNE Loop while not Equal
LOOPZ Loop while Zero

LOOP/LOOPnn Short-address

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If the value in CX register is nonzero, control jump to the operand address, but if the value in CX reaches zero, control will go to the next instruction (after the loop instruction).

LOOPZ/LOOPE (Loop while zero/equal) will continue looping while the CX register is zero or a zero condition is set.

LOOPNZ/LOOPNE (Loop while not zero/equal) will continue looping while the value in the CX register is not zero or a zero condition is not set.

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Example: (LOOP instruction)
Table 10.4
SSK 3207 – Chapter 11

11.6) Unconditional Transfer Instructions
The following are unconditional transfer instructions:

This chapter will only discuss on JMP instruction.

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Instructions Description Instructions Description
CALL Call a Procedure JMP Unconditional Jump
INT Interrupt RET Return
IRET Interrupt Return RETN/RETF Return Near/Far

[Label: ] JMP Short/Near/Far Address

Address for the jump instruction can be either short, near or far.
The jump instruction can be to the front or to the back as the following examples.

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11.7) Conditional Transfer Instructions
Table below shows the types of conditional transfer instructions.

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Instruction Description Flag Tested
JE/JZ Jump Equal or Jump Zero ZF
JNE/JNZ Jump Not Equal or Jump Not Zero ZF
JA/JNBE Jump Above or Jump Not Below/Equal CF, ZF
JAE/JNB Jump Above/Equal or Jump Not Below CF
JB/JNAE Jump Below or Jump Not Above/Equal CF
JBE/JNA Jump Below/Equal or Jump Not Above AF, CF

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Below is the format for Jnnn instructions.

The LOOP A20 instruction in Table 10.4, can be replaced by using the conditional instruction, JNZ A20 and DEC CX as in Table 10.5.

conditional jump instructions usually used with other instructions: CMP, INC, DEC etc.

Table 10.6, Table 10.7 and Table 10.8 are examples of conditional jump instruction.

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[Label: ] Jnnn Short-address

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Table 10.5
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CMP AL, 0 ; If AL = 000000002 then ZF = 1
JZ next ; Jump to next if ZF = 1
MOV BH, AL
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next: INC AL
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CMP AL, BL ; If AL = BL then ZF = 1
JE same ; Jump to same if ZF = 1
DEC BL
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same: MOV AL, BL
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Table 10.6
Table 10.7
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CMP AL, BL ; If AL = BL then ZF = 1
JNE same ; Jump to same if ZF = 0
DEC BL
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same: MOV AL, BL
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Table 10.8
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11.8) Other Instructions
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