CS计算机代考程序代写 cache assembly Chapter 1

Chapter 1

Chapter 2
Central Processing
Unit (CPU)

Topics
2.1 CPU Structure
2.2 Register Structure
2.3 Instruction Cycle

2.1 CPU Structure
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Figure 2.1 is the simplest possible depiction of the Central Processing Unit (CPU)
Early days – single CPU
In Modern days – increasing use of multiple processors in a single computer
CPU consist of three basic components namely Control Unit, Arithmethic & Logic Unit (ALU) and Registers

Figure 2.1 The Central Processing Unit (CPU)

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2.1 CPU Structure (cont..)

Control Unit
Several approaches to the implementation of the control unit.
Most commonly used is microprogrammed implementation
Microprogrammed control unit operates by executing microinstructions that define the functionality of the control unit.
Figure 2.2 shows the structure of control unit.
Figure 2.2
Microprogram – a sequence of microinstruction
Microinstruction – an instruction that controls data flow and sequencing in a processer

Control
Memory
Control Unit
Registers and
Decoders
Sequencing
Logic
Control Unit

Directs the entire computer system to carry out stored program instruction
Must communicate with both the arithmetic logic unit (ALU) and main memory
The control unit instructs the arithmethic logic unit that which logical or arithmetic operation is to be performed
Coordinated the activities of the other two units as well peropheral and auxiliary device linked to the computer

2.1 CPU Structure (cont..)
Control Unit

2.1 CPU Structure (Cont..)

As a temporary storage in CPU
Also known as high speed memory
Its function is to temporarily hold data and instructions that are taken from other components (example MM, I/O U, cache etc) to be processed in the CPU
Register

2.1 CPU Structure (cont..)

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations.
It represents the fundamental building block of the central processing unit (CPU) of a computer.
Modern CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs contain a control unit (CU).
Most of the operations of a CPU are performed by one or more ALUs, which load data from input registers.
A register is a small amount of storage available as part of a CPU. The control unit tells the ALU what operation to perform on that data and the ALU stores the result in an output register. The control unit moves the data between these registers, the ALU, and memory

ALU

2.2 Register Structure
The registers in the processor perform 2 roles:

User-visible registers – enable the machine- or assembly language programmer to minimize main memory references by optimizing use of registers. (will be discussed in chapter 8-9)

Control and status registers – used by the control unit to control the operation of the processor and by privileged, operating system program to control the execution of program.
(eg: PC, MAR, MBR and IR)
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Figure 2.3 illustrates top level view of computer components and suggests the interactions among them.
Instruction processing consist of two steps. The processor reads (fetches) instructions from memory one at a time and executes each instruction
Program execution consists of repeating the process of instruction fetch and instruction execution

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2.2 Register Structure

2.3 Instruction Cycle
The processing required for a single instruction is called an instruction cycle
The function of computers is to execute programs.
Programs comprise a set of instructions and data that is stored in the main memory.
Every instruction will be taken and executed by the CPU one by one until all of them are executed.

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2.3 Instruction Cycle (cont..)
The process of executing a single instruction is called Instruction Cycle which can be divided into:
Fetch Cycle
read the next instruction from MM into the CPU.
2. Execute Cycle
interpret the opcode and perform the indicated operation.
Figure 2.4 Basic Instruction Cycle
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2.3 Instruction Cycle (cont..)
Figure 2.5 Basic Instruction Cycle

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Figure 3.2 illustrates these top-level components and suggests the interactions among them. The CPU exchanges data with memory. For this purpose, it typically makes use of two internal (to the CPU) registers: a memory address register (MAR), which specifies the address in memory for the next read or write, and a memory buffer register (MBR), which contains the data to be written into memory or receives the data read from memory. Similarly, an I/O address register (I/OAR) specifies a particular I/O device. An I/O buffer register (I/OBR) is used for the exchange of data between an I/O module and the CPU. A memory module consists of a set of locations, defined by sequentially numbered addresses. Each location contains a binary number that can be interpreted as either an instruction or data. An I/O module transfers data from external devices to CPU and memory, and vice versa. It contains internal buffers for temporarily holding these data until they can be sent on. Having looked briefly at these major components, we now turn to an overview of how these components function together to execute programs.
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Fetch Cycle
The process of fetching an instruction from MM into the CPU
4 registers are involved:
i. PC (Program Counter)
– Temporary hold the address of an instruction (in MM) that
has to be fetched and executed in the CPU
ii. MAR (Memory Address Register)
– A register that connected to the MM through the address bus.
– Temporary hold the address of an instruction from the PC.
– The content in PC will be transferred into the
MAR and then to the address bus and to the
location in MM that pointed by the address given.
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2.3 Instruction Cycle (cont..)

iii. MBR (Memory Buffer Register)
– A register that connected to the MM through
the data bus
– Used to temporary hold instruction or data taken from
the MM or data that will be moved into the
MM or other computer components after
being processed by the CPU.

iv. IR (Instruction Register)
– Used to temporary hold instruction (operation code)
before it is being decoded by the Instruction
Decoder inside the control unit.
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Fetch Cycle
2.3 Instruction Cycle (cont..)

Generally the process in the Fetch Cycle can be depicted by:
MAR ← PC (specify address in MM for the next read/write)
MBR ← M (MAR) (data to be written/received from memory)
PC ← PC + 1 (hold address to be fetched next. CPU increment the PC after each instruction)
IR ← (MBR) (fetched instruction is loaded into register)
2.3 Instruction Cycle (cont..)
Fetch Cycle
Figure 2.4 Basic Instruction Cycle

2.3 Instruction Cycle (cont..)

Fetch Cycle

Execute Cycle
The process of executing the instruction that has been fetched earlier in fetch cycle.
The followings are the steps that involve in the execute cycle:

1. Instruction decoding (to determine the
operation that has to be performed by the CPU)
2. Operand (data) fetching
3. Data Processing
4. Store Result
 The sequences of operations that happen in execution cycle differ according to the type of instruction.

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2.3 Instruction Cycle (cont..)

Example: ADD R1, X
This instruction adds the content in the R1 register with the content in the MM at location X and the result is stored in the R1 register, i.e.: R1 ← R1 + M (X)
(Observe the diagram above)
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Execute Cycle
2.3 Instruction Cycle (cont..)
Figure 2.6

Before the addition operation is performed in the ALU, the required data is taken and moved into a register in the CPU
The data in R1 is already in the CPU (R1 is one of the registers in CPU)
The addition operation is performed in ALU and the result is stored in the R1 register
The process which takes place in the Execution Cycle for instruction ADD R1,X can be depicted by:

MAR ← IR (address X)
MBR ← M (MAR)
R1 ← R1 + MBR
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2.3 Instruction Cycle (cont..)

Figure 2.7 Instruction Cycle State Diagram
Figure 2.7 is a more detailed look at the basic instruction cycle of Figure 2.4.
The figure is in the form of a state diagram.
For any given instruction cycle, some states may be null and others may be visited more than once.

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2.3 Instruction Cycle (cont..)

2.3 Instruction Cycle (cont..)

The states can be described as follows:
Instruction address calculation (iac): Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of the previous instruction. For example, if each instruction is 16 bits long and memory is organized into 16-bit words, then add 1 to the previous address. If, instead, memory is organized as individually addressable 8-bit bytes, then add 2 to the previous address.
Instruction fetch (if): Read instruction from its memory location into the processor.
Instruction operation decoding (iod): Analyze instruction to determine type of operation to be performed and operand(s) to be used.

Instruction Cycle State

2.3 Instruction Cycle (cont..)
Operand fetch (of): Fetch the operand from memory or read it in from I/O.
Data operation (do): Perform the operation indicated in the instruction.
Operand store (os): Write the result into memory or out to I/O.

Instruction Cycle State

2.3 Instruction Cycle (cont..)

2.3 Instruction Cycle (cont..)
Three instructions, which can be described as three fetch and three execute cycles, are required:

Figure 2.7 Example of Program Execution
(contents of memory and registers in hexadecimal)

Figure 3.5 illustrates a partial program execution, showing the relevant portions of memory and processor registers.1
The program fragment shown adds the contents of the memory word at address 940 to the contents of the memory word at address 941 and stores the result in the latter location

2.3 Instruction Cycle (cont..)

Partial program execution example

2.3 Instruction Cycle (cont..)

Exercise
The hypothetical machine of figure 3.4 also has two I/O instructions:
0011= Load AC from I/O
0111= Store AC to I/O
In these cases the 12-bit address identifies a particular I/O device. Show the program execution (using format of figure 3.5) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.

Assume that the next value received from device 5 is 3 and that location 940 contains value of 2.

Solution
Step 1
We will assume that the memory (contents in hex) as the previous table:
300: 3005; 301: 5940; 302: 7006
Therefore, the steps will be as the following:
Step 1: 3005 → IR
Step 2: 3 → AC
Step 3: 5940 → IR
Step 4: 3 + 2 = 5 → AC
Step 5: 7006 → IR
Step 6: AC → Device 6

Solution
Step 2
Explanation
Instruction register (IR) is the one which stores instruction currently being executed or decoded
Program Counter (PC) is the one that holds address of the instruction being executed at current time
12 bits is used to specify the address and 4 bits in the IR indicates accumulator to be loaded
Lets the content of memory be
300:3005
301:5940
302:7006

Solution
Step 3
In step1 the “Program Counter” holds the value of “300” and “Instruction register” holds contents of address “300” that is “3005”

Solution
Step 4
The content of address location “005” is moved to the accumulator and instruction register holds the value “5940”

Solution
Step 5
Add contents of Accumulator with contents of address “940” and stored back to accumulator

Solution
Step 6
The next instruction (7006) is fetched from location 302 and PC is incremented

Solution
Step 7
The contents of the AC are stored in location 006