CS计算机代考程序代写 Chapter 4  

Chapter 4  

SSK3207 – Chapter 8
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Chapter 8
 

Combinational and Sequential Circuit

SSK3207 – Chapter 8
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Topics
8.1  Combinational Circuit and Sequential Circuit

8.2   Examples of Combinational
Circuit

8.3   Examples of Sequential Circuit

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8.1) Combinational Circuit and Sequential Circuit

Logic Circuits can be divided into :
1.      Combinational Logic Circuit
2.      Sequential Logic Circuit

1. Combinational Logic Circuit
 contains logic gates where its output is determined by the combination of the current input, regardless of the output or the prior combination of input.

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 combinational circuit can be depicted by Diagram 1 below:
n input
m output
combinational circuit
 Examples of combinational circuits in the computer
system are decoder, parallel adder, and multiplexer.
 
(Note: Students are encouraged to obtain examples of combinational circuits stated above)
 

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2. Sequential Logic Circuit

 Sequential Logic Circuit contains logic gates arranged in parallel and its output is not only determined by the combination of the current input, but also the prior output.

 The circuit also contains memory elements that enable it to store the information of the prior output.

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 Examples of sequential circuits in the computer
system are registers, counters and serial adders.

n input
m output
sequential
logic
circuit
memory elements

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8.2) Examples of Combinational Circuit

The circuits in chapter 6 are combinational circuits.
The steps to design combinational circuits are as the following:
1.  Determine the problem
2. Determine the number of input and output that are needed
3.  Give symbols for the stated input and output
4.  Construct a truth table that defines the relationship between the input and output

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5.  Obtain the Boolean function or the logical expression from the truth table in (4) using Karnaugh Map or other known methods.
6.  Draw a logic circuit based on the expression obtained from (5) above.

Example 1:
Chapter 6.7 : Alarm System

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8.2.1) Adder
ADDER is an example of a combinational logic circuit in a computer system

one of the components in an ALU, CPU to add two binary numbers.

two types of addition:

 Half addition: addition of 2 bits data input and produce 2 bits output, the result and the carrier.

 A logic circuit for half addition is known as Half Adder

  Full Addition: addition of 3 bits data input (2 bits data and 1 bit carrier) and produce 2 bits output, the result and the carrier.
 A logic circuit for full addition is known as Full Adder

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HALF ADDER

2 BITS INPUT
2 BITS OUTPUT

FULL ADDER

3 BITS INPUT
2 BITS OUTPUT

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A Logic Circuit for Half Adder (HA)

The steps to design:
   Problem: to design a logic circuit for an addition of 2 bits data input.

 Number of input : 2
Number of output : 2

 Variables for input : x and y
Variables for output : s (sum) and c (carry)

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The Truth Table for the problem :

INPUT

OUTPUT

x

y

s

c

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

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0 1
0

1
x
y
1
1

_ _
s = x y + x y
= x  y
For s

0 1
0

1
x
y
1

c = x y
For c
 Using Karnaugh Map to get the logic expressions for s and c.

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 A logic circuits for Half Adder

x
y
_ _
s = xy + xy
c = xy
OR

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A Block Diagram for HA is as below:
x
y
x  y = s
xy = c
x
y
s
c
HA
input
output

SSK3207 – Chapter 8
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A Logic Circuit for Full Adder (FA)

The same method is used as to design Half Adder.

 Problem: Build logic circuit for the addition of 3 bits data input and produce 2 bits data output.

 Number of input : 3
Number of output : 2

 Variables for input: x , y and ci (carrry in)
Variables for output : s (sum) and co (carry out)

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 The truth table for the problem is as follow:
INPUT

OUTPUT

x

y

ci

s

co

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

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 Obtain the expression for r and co using Karnaugh Map (Students are required to try this out themselves):
 
s = x y pi + x y ci + x y ci + x y ci
= x  y  ci

and co = x y + y ci + x ci

 Draw the circuit for FA (Students are required to try this out themselves)

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Below is a block diagram for FA (3 inputs and 2 outputs)

x
y
s
FA
input
output
co
ci

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 To construct a 4-bit parallel adder, 3 FA and 1 HA are required.

 Diagram below is a block diagram of 4-bit parallel adder with X = x3x2x1x0 and Y = y3y2y1y0 (X and Y are 4-bit binary numbers) as the input and the output (addition result) is s3s2s1s0.

X = x3x2x1x0
+ Y = y3y2y1y0
S = s3s2s1s0

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x3 y3
FA
FA
FA
HA
x2 y2
x1 y1
x0 y0
c3 s3
c0
s0
c2
c1
s2
s1
INPUT
OUTPUT

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OR
0

x3 y3
FA
FA
FA
FA
x2 y2
x1 y1
x0 y0
c3 s3
c0
s0
c2
c1
s2
s1
INPUT
OUTPUT

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8.3) Examples of Sequential Circuits

Sequential circuits are a kind of logic circuit where the current outputs are not only depend on the current inputs but also the past history of inputs (previous outputs).

In generally, the current outputs of a sequential logic circuit are depending on the current inputs and also the current state of that circuit.

past history of inputs = previous outputs
= the current state of the circuit

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 It is also known as 1-bit memory element and is mostly used to make important computer components such as registers, counters, memory etc.
 The simplest form of sequential circuit is the flip-flop. Flip-flop is a kind of logic circuit that is capable of exhibiting 2 stable conditions.

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There are a variety of flip-flops, all of which share two properties:

 The flip-flop is a bistable device and has a value either 0 or 1. It exists in one of two states and, in the absence of input, it remains in that state. Thus, the flip-flop can function as a 1-bit memory.

 The flip-flop has two outputs, which are always the complements of each other. These are generally labelled Q and Q.

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 Sequential circuits can be divided into:
  1. Synchronous
2. Asynchronous

 In synchronous sequential circuit, all flip‑flops are moved by the same clock pulse so that all flip‑flops involved change simultaneously.

 In asynchronous circuit, the change of flip‑flop condition depends on the change that occurs on the input and the late time that is in the circuit.

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8.3.1) S‑R Flip‑flop

S‑R flip‑flop has 2 inputs, S (set) and R (reset).

Diagram 1 below is a block diagram of S-R flip-flop.

In Diagram 1 , there is another input called clock to control the movement of the input that is input will only occurs when the circuit is given a clock pulse (synchronous circuit)

 The features of S‑R flip‑flop can be depicted in Table 1 below. It can be summarized that:

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 If the values of both S and R are 0, the flip‑flop will remain in its present state (either 0 or 1).

 If S = 0 and R = 1 (reset), then the state of the flip‑flop will change to 0 (its output, Q = 0 (reset)).

 If S = 1 (set) and R = 0, then the state of the flip‑flop will change to 1 (output, Q = 1 (set)).

 This circuit does not allow the combination of input S = 1 and R = 1.

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Diagram 1 : S-R Flip-flop
Table 1 : Feature table
of S-R Flip-flop

clock
S
R
Q

Q
S

R

Qn

Qn+1

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

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8.3.2) J-K Flip-flop

 J-K flip-flop also has 2 inputs, J and K. The function of clock is same as S‑R flip‑flop. Unlike S‑R flip‑flop, J‑K flip‑flop allows all combination of inputs.

The logic circuit for J-K flip-flop is shown in Diagram 2 below.

Table 2 shows the features of the J‑K flip‑flop. From Table 2, it can be summarized that:

 

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 If J = 1 and K = 1, it will change the state of the flip‑flop that is it will become complementary to the initial or prior state (0  1 or 1  0)
 

 If J = 0 and K = 0, it will maintain the state of the flip‑flop (either 0 or 1).

 If J = 0 and K = 1, it will cause flip‑flop to change to state 0 (reset).

 If J = 1 and K = 0, it will cause flip‑flop to change to state 1 (set).

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Clock
J
K
Q

Q
Diagram 2: J-K Flip-flop
Table 2: Features table of
J-K flip-flop

J

K

Qn

Qn+1

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

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8.3.3) D Flip‑flop
Logic circuit for D flip‑flop is shown in Diagram 3 below. This flip‑flop only has one input , that is D.

The features of D flip‑flop can be illustrated by Table 3.

From Table 3, it shows that the output of the D flip‑flop is the same as its input regardless of the previous state of the flip-flop.

This feature is very suitable to be used as a memory element and this flip-flop is mostly used to make CPU registers and computer memory (RAM).

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Diagram 3 : D Flip-flop
Table 3 : Feature table of
D Flip-flop

clock
D
Q

Q

D

Qn

Qn+1

0

0

0

0

1

0

1

0

1

1

1

1

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8.3.4) Register and Serial Adder

As priory stated, flip-flop is an example of the simplest form of sequential circuit. It is also a form of memory element where a flip-flop can store 1 bit of data.

In this section, examples of sequential circuits that use flip-flop will be given:

1. Register
2.  Serial Adder
  

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Register

Register is one of the CPU component . Generally it can be categorized into:
 Storage Register (or Parallel Register)
 Shift Register (or Serial Register)

Data in the parallel register can be written on and read out simultaneously. MAR, MBR and IR are examples of parallel registers.

The number of flip-flop that used in the register is depend on the size of the register (8-bit register = 8 flip-flop)

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 Parallel or Storage Register

Diagram 4 below is a 4-bit parallel register that uses D flip-flop.

In Diagram 4, 4 bits input is admitted simultaneously into a different flip-flop, that is I1, I2, I3 and I4, whereas its output is also simultaneously or parallel going out from different flip-flop, that is Q1, Q2, Q3 and Q4.

(Note: all kinds of flip-flop can be used to design a parallel register, but its circuit will differ because different flip-flop has different features)

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Diagram 4: A 4-bit parallel register that uses D Flip-flop

Clock
D
Q

I2

Clock
D
Q

I1

Clock
D
Q

I4

Clock
D
Q

I3

Q1
Q2
Q3
Q4

Clock
Pulse

_
Q
_
Q
_
Q
_
Q

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Serial or Shift Register

In shift register, only one output is produced at a time.

There are 2 types of shift register:
 shift to the right (shift-right)
 shift to the left (shift-left).

Shift-right register means the input will be inserted into the leftmost flip-flop and the output will be going out from the rightmost flip-flop.

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Output
Diagram 5: 4-bit Shift -Right Register Using J-K Flip-flop
Diagram 5 below is an example of 4-bit shift-right register using J-K flip-flop.

Clock
J
Q
K

Clock
J
Q
K

Clock
J
Q
K

Clock
J
Q
K

Input
Clock
Pulse
_
Q
_
Q
_
Q
_
Q

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 Serial Adder

 There are 2 types of adder:
 Parallel Adder
 Serial Adder

Parallel adder is an adder that performs addition concurrently for every bits.

Adder in section 7.2.1 is called a parallel adder.

Serial Adder performs an addition bit by bit starting from the rightmost bit.

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Diagram 6 below is an example of a 4-bit serial adder.

This 4-bit serial adder uses two 4-bit shift-right registers, X and Y to temporarily hold operand 1 (X = x3x2xIx0) and operand 2 (Y = y3y2y1y0), a full adder and a D flip‑flop (to hold the carrier value).

The addition process in the adder is as below :
X = X + Y
  that is the X and Y registers will hold operand 1 and operand 2 and the addition result will be kept back in the X register.

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Hence, in the addition, the value in the Y (Operand 2) register will be remained while the value or data in the X register will be changed to the result of X+Y after the addition complete. (the value of operand 1 will be lost)
 
Note: observe and understand the data movement in the serial adder after every clock pulse is given.

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Diagram 6 : 4-bit Serial Adder
x3
x2
x0
x1
y3
y2
y0
y1

Full
Adder
xi
yi
ci

ci+1
si

D flip-flop
Carry

Y Register
X Register
Clock Pulse