2021 COMP3222/9222 Practical Exam Instructions
How will the exam be conducted?
• The Final Practical exam will be held on the afternoon of Monday 29 November.
• The exam will be held from 3:00 pm until 5:20 pm on WebCMS.
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• There are 4 questions in total.
• The exam is worth 30 marks in total. The exam contributes 30% to your final
assessment in the course. You must score at least 40% of the available marks in this
exam in order to pass the course.
• The exam has a 140 minute time limit (consideration for 10 minutes reading time
and time to upload files with momentary glitches in connectivity are included in this
time allowance).
• All times stated for the exam are in Sydney time (AEDT = UTC+11).
What exam materials can be used?
• Make sure you have a quiet location with good internet connectivity where you can work on the exam undisturbed for the full 140 minutes.
• No exam materials are provided. You will need paper and pens and a means of scanning and uploading answers to some of the questions.
• You may use any offline resources, including your course notes, personal notes, textbooks, and lab files.
• You are not permitted to access web pages or other internet resources, except for the course and exam web pages
• You are not permitted to use code-synthesis tools such as GitHub Copilot
• Do not place your exam work in any location, including file sharing services such as
Dropbox or GitHub, accessible to any other person.
• You may not request help from any person or service apart from the Course Coordinator, who will be available by email and on Teams.
• Even after you finish the exam, on the day of the exam do not communicate your exam answers to anyone. Some students have extended time to complete the exam.
• Ensure during the exam no other person in your household can access your work.
• Your zpass should not be disclosed to any other person. If you have disclosed
your zpass, you should change it immediately.
• Deliberate violation of exam conditions will be referred to Student Integrity as
serious misconduct
Useful advice from UNSW on open book exams
https://www.student.unsw.edu.au/open-book-and-take-home-exams
• Please ensure that you upload files, where required, as you progress through the exam – submissions will not be permitted after the time allowed for the exam has expired.
• Please note that only your last submission for each part will be marked.
2021 COMP3222/9222 Practical Exam 1
No help is allowed during the exam
• You must not communicate with anyone while you are taking the exam.
• You are not permitted to use any online resources, e.g. searching for answers to
questions using the Internet.
• Failure to comply with the above, if detected, will result in disciplinary action.
• If you experience difficulties during the exam, or have a question about the exam,
contact the Course Coordinator by email or via Teams as soon as possible.
Technical issues
If you experience a technical issue before or during the exam, you should follow these instructions:
• Take screenshots of as many of the following as possible: o error messages
o screen not loading
o timestamped speed tests
o power outage maps
o messages or information from your internet provider regarding the issues
experienced
• All screenshots must include the date and time the issue occurred.
• Contact the Course Coordinator by phone (+61 2 9385 7384) email
or via Teams immediately and advise of the issue.
• Submit a Special Consideration application immediately at the conclusion of your
assessment and upload your screenshots.
Academic misconduct & Plagiarism
• You must treat this exam as you would treat an in-person, supervised and
invigilated exam. Any evidence of academic misconduct will be treated seriously. Student Declaration
You will complete a digital declaration prior to commencing the exam. By completing the declaration you are declaring that:
• As with any task conducted through UNSW, I am aware that online assignments and examinations require me to comply with the UNSW Student Code of Conduct (https://student.unsw.edu.au/conduct).
• I have read and understood the University requirements in respect of student academic misconduct outlined in the Student Code of Conduct (https://student.unsw.edu.au/conduct) and Annexure 1 of the Student Misconduct Procedures (https://www.gs.unsw.edu.au/policy/documents/studentmisconductprocedures.pdf )
• It represents my own work and that I did not give or receive assistance in any way that would violate the UNSW Student Code of Conduct (https://student.unsw.edu.au/conduct),
• I have taken proper and reasonable care to prevent this work from being copied by another student
2021 COMP3222/9222 Practical Exam 2
• I understand the following actions, among others, constitute Academic Misconduct: o Allowing others to complete an online task in my place, either in whole or in
o Taking or sharing screenshots of the assessment task or my responses
unless expressly permitted by UNSW.
o Otherwise duplicating or distributing the assessment task in whole or in
o Communicating any assessment content, question or topic to any person
prior, during or following the assessment unless expressly permitted by
o Providing or seeking assistance from unauthorised information sources
including, but not limited to, the Internet, any programs, chat servers, web services, or contact with any external parties to communicate, collude or get assistance in answering examination questions either prior to or during an online exam session.
• I understand any breach of the above terms and conditions may result in university disciplinary action.
Special consideration
• This exam is covered by UNSW’s Fit-to-Sit policy. That means that by sitting this exam, you are declaring yourself well enough to do so. You will be unable to apply for special consideration after the exam for circumstances affecting you before it began. If you have questions, or you feel unable to complete the exam, contact the Course Coordinator by phone (+61 2 9385 7384) email or via Teams
2021 COMP3222/9222 Practical Exam 3
PROBLEM SPECIFICATION
In this problem, you are required to design and implement a simple stack-based calculator. You are required to design a circuit that implements a 4-entry, 4-bit stack that allows 4-bit unsigned addition and subtraction to be performed on the topmost two entries of the stack.
This design implements the basic requirements of a calculator that uses Reverse Polish Notation (postfix notation), as popularized by Hewlett-Packard.
The detailed requirements of the design are as follows (refer to Figure 1):
Figure1. Stack-based calculator circuit.
• The design uses a free running 50 MHz clock
• Let the 4 entries of the stack be denoted STACK3 – STACK0, whereby STACK3
corresponds to the Top of Stack (TOS)
• Each entry of the stack is 4-bits wide and can therefore store unsigned numerical
values 0 – 15
• The contents of the stack are continuously displayed in hexadecimal notation using the
7-segment displays; the contents of STACK3 (TOS) are displayed in HEX3, STACK2 in
HEX2, and so on for the remaining entries
• The stack is asynchronously cleared/reset at any time by pressing KEY[0]
(BUTTON0/KEY0 on the DE0/DE1 board); the stack is cleared by having each entry set
• After the circuit has been reset, the operator can push a num onto the stack, pop the
Top of Stack, and add or subtract the contents of the top two stack entries by selecting the desired operation using the SW[9:8] switch settings and pressing KEY[2] to execute the operation. These operations may be requested in any order and have the semantics given below:
push A value is “pushed” onto the stack by setting switches SW3-SW0 (num), setting switches SW[9:8] = “00” and pressing KEY[2]; “pushing” a value onto the stack results in the following register transfers: STACK0 STACK1, STACK1 STACK2, STACK2 STACK3, STACK3 num, i.e. shift stack contents as seen on the 7-segment displays RIGHT and set TOS to num
pop The TOS is “popped” by setting switches SW[9:8] = “01” and pressing KEY[2]; “popping” the stack results in the following register transfers: STACK3 STACK2, STACK2 STACK1, STACK1 STACK0, STACK0 0, i.e. shift stack contents as seen on the 7-segment displays LEFT and set STACK0 to 0
add The top two stack entries are added together by setting switches SW[9:8] = “10” and pressing KEY[2] to effect the following register transfers: STACK3 STACK2 + STACK3, STACK2 STACK1, STACK1 STACK0, STACK0 0;
2021 COMP3222/9222 Practical Exam 4
addition is unsigned, and therefore performed modulo 16
subtract TOS is subtracted from STACK2 by setting switches SW[9:8] = “11” and
pressing KEY[2] to effect the following register transfers: STACK3 STACK2 – STACK3, STACK2 STACK1, STACK1 STACK0, STACK0 0; subtraction is unsigned, and therefore performed modulo 16
• Each requested operation is performed only once per press of KEY[2]. The operation may be performed on the first positive clock edge after the button is pressed, or on the cycle afterwards.
• Once powered on, the circuit performs the requested sequence of operations until it is powered off again.
• KEY[0]/KEY[2] refers to BUTTON0/BUTTON2 on the DE0 board, and KEY0/KEY2 on the DE1.
• Recall that the push buttons are pulled low, i.e. provide a 0 input when they are pressed.
A simulation of the stack-based calculator is illustrated in Figure 2. Note that in the illustration of the simulation, the waveforms SW[9] & SW[8] correspond to the high and low bits of the op_select signal, KEY[0] corresponds to the reset button signal, and KEY[2] corresponds to the execute button signal. The stack contents are illustrated for a sequence of operations. Note that the long KEY[2] button press that extends over several clock cycles at 320 ns only results in a single push operation.
Figure 2. Simulation of the calculator circuit.
You are provided with a Quartus Project Archive with pin assignments that map the circuit to the board you are using. The archive is named DEn-calc.qar, whereby you should use the archive named for the board you are using: n = 0 for DE0 and n = 1 for DE1. The archive contains outlines of the top-level, data and control paths for this problem, the waveform file used to generate the timing diagram above, as well as a solution bitstream you may use to check the intended operation of the circuit. The archive contents are listed at the end of this specification.
Please ensure that you download and use the correct archive for the board you are using!
2021 COMP3222/9222 Practical Exam 5
Submission
Please upload your files regularly.
This will avoid delays when students submit simultaneously at the end of the exam. Please note that only your last submission will be marked.
YOU MUST SUBMIT YOUR WORK WITHIN THE TIME ALLOWED.
Late submissions WILL NOT be accepted.
You are required to submit:
1. [5 marks]
A neat & legible listing of the pseudocode for this problem and a neat & legible sketch of your initial ASM chart for your design. Please take care with Mealy & Moore type outputs.
2. [4 marks]
A neat & legible sketch of the datapath for your design. The sketch MUST indicate the name of all signals as used in your VHDL description and correspond with the names used in your refined ASM chart of 3. Your datapath sketch MUST indicate the number of bits used for each signal and the size of all components.
3. [3 marks]
A neat & legible sketch of a refined copy of your ASM chart from 1. This diagram MUST use the same signal names and state names as used in your VHDL description and MUST indicate the state transitions and outputs of the control path.
4. [18 marks]
A Quartus Project Archive of your completed design. To facilitate testing, do not modify
the top-level ENTITY description for calc.
Your solution will be marked according to the following scheme:
a. [15 marks]
Still testing and debugging VHDL code – we will assess the completeness and correctness of your description.
b. [2 marks]
Simulation complete – make sure we have your waveform file in the directory as we will check your simulation progress.
Upload a SINGLE PDF, JPG or PNG format file containing your answer using the WebCMS
submission tab for Part 1. of the exam.
2021 COMP3222/9222 Practical Exam 6
Upload a SINGLE PDF, JPG or PNG
format file containing your answer using the WebCMS submission tab for Part 2. of the
Upload a SINGLE PDF, JPG or
PNG format file containing your answer using the WebCMS submission tab for Part 3. of
your answer using the WebCMS submission tab for Part 4. of the exam.
Upload a SINGLE QAR format file containing
c. [1 marks]
Implementation complete – we will test your design on the board.
You may find that it simplifies your task to develop a solution in two stages:
• First, design, test and implement the stack and the push & pop operations.
• Then, supplement the design with the mathematical operations add and
Quartus Project Archive contents
calc-solution.sof
controlpath.vhd
datapath.vhd
package.vhd
Description
sample solution bitstream
project file
device and pin assignments top-level design file stub
simulation waveform control path design file stub datapath design file stub subcomponent package 7-segment display encoder
You may need to “add file” in the Programmer pop-up to select this file
To be modified by you
Do not modify the ENTITY description for calc
To be modified by you To be modified by you To be modified by you
2021 COMP3222/9222 Practical Exam
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