— =============================================================================================================
— *
— * Copyright (c) Mike
— *
— * File Name: clock_10MHz.vhd
— *
— * Version: V1.0
— *
— * Release Date:
— *
— * Author(s): M.Freeman
— *
— * Description: 10MHz clock wrapper
— *
— * Conditions of Use: THIS CODE IS COPYRIGHT AND IS SUPPLIED “AS IS” WITHOUT WARRANTY OF ANY KIND, INCLUDING,
— * BUT NOT LIMITED TO, ANY IMPLIED WARRANTY OF MERCHANTABILITY AND FITNESS FOR A
— * PARTICULAR PURPOSE.
— *
— * Notes:
— *
— =============================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity async_reset is
Port ( clk : in STD_LOGIC;
locked : in STD_LOGIC;
reset_in : in STD_LOGIC;
reset_out : out STD_LOGIC;
reset_out_n : out STD_LOGIC );
end async_reset;
architecture async_reset_arch of async_reset is
constant SIZE : integer := 4;
signal reset_internal : std_logic_vector(SIZE downto 0);
signal full : std_logic_vector(SIZE downto 0);
begin
full <= (others => ‘1’);
reset_shift_reg : process ( clk, reset_in )
begin
if reset_in = ‘1’
then
reset_internal <= (others =>‘0’);
elsif clk=’1′ and clk’event
then
if locked = ‘1’
then
reset_internal(0) <= '1';
for I in 0 to SIZE-1
loop
reset_internal(SIZE-I) <= reset_internal(SIZE-I-1);
end loop;
else
reset_internal <= (others =>‘0’);
end if;
end if;
end process;
reset_gen : process( clk )
begin
if clk=’1′ and clk’event
then
if reset_internal /= full
then
reset_out <= '1';
reset_out_n <= '0';
else
reset_out <= '0';
reset_out_n <= '1';
end if;
end if;
end process;
end async_reset_arch;