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— “Output Output Phase Duty Pk-to-Pk Phase”
— “Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)”
——————————————————————————
— CLK_OUT1____10.000______0.000______50.0______467.358____318.001
—
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— “Input Clock Freq (MHz) Input Jitter (UI)”
——————————————————————————
— __primary_________100.000____________0.010
— The following code must appear in the VHDL architecture header:
————- Begin Cut here for COMPONENT Declaration —— COMP_TAG
component clock10MHz
port
(– Clock in ports
CLK_IN1 : in std_logic;
— Clock out ports
CLK_OUT1 : out std_logic;
— Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
— COMP_TAG_END —— End COMPONENT Declaration ————
— The following code must appear in the VHDL architecture
— body. Substitute your own instance name and net names.
————- Begin Cut here for INSTANTIATION Template —– INST_TAG
your_instance_name : clock10MHz
port map
(– Clock in ports
CLK_IN1 => CLK_IN1,
— Clock out ports
CLK_OUT1 => CLK_OUT1,
— Status and control signals
RESET => RESET,
LOCKED => LOCKED);
— INST_TAG_END —— End INSTANTIATION Template ————