Xilinx System Settings Report
System Settings
Environment Settings
Environment Variable xst ngdbuild map par
LD_LIBRARY_PATH /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin:
/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin/installed_lin/lib:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin < data not available > < data not available > < data not available >
LMC_HOME /opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin/installed_lin < data not available > < data not available > < data not available >
PATH /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin32_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin32_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin:
/home/mike/bin:
/home/mike/.local/bin:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games < data not available > < data not available > < data not available >
XILINX /opt/Xilinx/14.7/ISE_DS/ISE/ < data not available > < data not available > < data not available >
XILINX_DSP /opt/Xilinx/14.7/ISE_DS/ISE < data not available > < data not available > < data not available >
XILINX_EDK /opt/Xilinx/14.7/ISE_DS/EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD /opt/Xilinx/14.7/ISE_DS/PlanAhead < data not available > < data not available > < data not available >
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn mux_2_12.prj
-ofn mux_2_12
-ofmt NGC NGC
-p xc7z010-3-clg400
-top mux_2_12
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {“ipcore_dir” }
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets Auto Auto
-fsm_extract YES Yes
-fsm_encoding Auto Auto
-safe_implementation No No
-fsm_style LUT LUT
-ram_extract Yes Yes
-ram_style Auto Auto
-rom_extract Yes Yes
-shreg_extract YES Yes
-rom_style Auto Auto
-auto_bram_packing NO No
-resource_sharing YES Yes
-async_to_sync NO No
-use_dsp48 Auto Auto
-iobuf YES Yes
-max_fanout 100000 100000
-bufg 32 32
-register_duplication YES Yes
-register_balancing No No
-optimize_primitives NO No
-use_clock_enable Auto Auto
-use_sync_set Auto Auto
-use_sync_reset Auto Auto
-iob Auto Auto
-equivalent_register_removal YES Yes
-slice_utilization_ratio_maxmargin 5 0
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i3-2350M CPU @ 2.30GHz/2203.277 MHz < data not available > < data not available > < data not available >
Host mike-SATELLITE-PRO-C850-10N < data not available > < data not available > < data not available >
OS Name LinuxMint < data not available > < data not available > < data not available >
OS Release Linux Mint 18.3 Sylvia < data not available > < data not available > < data not available >