sch2sym -intstyle ise -family zynq -w -refsym lifo_12 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sym
sch2sym -intstyle ise -family zynq -w -refsym lifo_12 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sym
sch2sym -intstyle ise -family zynq -w -refsym lifo_12 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/lifo_12.sym
sch2sym -intstyle ise -family zynq -w -refsym lifo_12 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/lifo_12.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/lifo_12.sym
sch2hdl -sympath /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/ipcore_dir -intstyle ise -family zynq -flat -suppress -vhdl lifo_12_drc.vhf -w /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/lifo_12.sch