Xilinx Design Summary
counter_12 Project Status (11/17/2019 – 21:04:12)
Project File: simple_cpu_v1d.xise Parser Errors: No Errors
Module Name: mux_2_16 Implementation State: Synthesized
Target Device: xc7z010-3clg400 Errors:
Product Version: ISE 14.7 Warnings:
Design Goal: Balanced Routing Results:
Design Strategy: Xilinx Default (unlocked) Timing Constraints:
Environment: Final Timing Score:
Detailed Reports [-]
Report Name Status Generated Errors Warnings Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report
Secondary Reports [-]
Report Name Status Generated
Date Generated: 11/17/2019 – 21:04:53