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/add_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|add_12.sch
/add_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|add_16.sch
/add_sub_8 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|add_sub_8.sch
/and_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|and_16.sch
/buf12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|buf12.sch/XLXI_2 – buf8
/buf8 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|buf8.sch
/computer |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers|VHDL|Src|computer.sch/CPU – simple_cpu_v1d
/computer |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers|VHDL|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_0 – alu
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/DATA_BUF – buf16
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/REG_FILE – register_file_4
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/MEM – ram_4Kx16 – ram_4Kx16_arch
/computer |home|mike|Documents|SYS1|Exam|VHDL|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_0 – alu
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/DATA_BUF – buf16
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/DECODE_LOGIC – control_logic
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/REG_FILE – register_file_4
/computer |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_0 – alu
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/CTL_LOGIC – control_logic
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/DATA_BUF – buf16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/DECODE_LOGIC – control_logic
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/REG_FILE – register_file_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/XLXI_48 – buf16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/XLXI_49 – register_file_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/MEM – ram_4Kx16 – ram_4Kx16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_0 – alu
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/REG_FILE – register_file
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/CPU – simple_cpu_v1d/XLXI_48 – buf16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/MEM – ram_4Kx16 – ram_4Kx16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_14 – ram_4Kx16 – ram_4Kx16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_26 – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_10 – reg_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_11 – add_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_15 – mux_2_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_16 – mux_2_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_17 – add_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_18 – lifo_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_29 – mux_3_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_30 – data_mux
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_37 – register_file
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_47 – control_logic
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_18 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_19 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_20 – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_22 – counter_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_23 – reg_24
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_26 – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_10 – reg_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_11 – add_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_11 – add_12/XLXI_1 – add_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_11 – add_12/XLXI_3 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_11 – add_12/XLXI_4 – add_8/XLXI_1 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_11 – add_12/XLXI_4 – add_8/XLXI_2 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_15 – mux_2_12/XLXI_1 – mux_2_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_27 – counter_12/XLXI_15 – mux_2_12/XLXI_3 – mux_2_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_28 – mux_2_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_57 – mux_3_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_57 – mux_3_16/XLXI_1 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_57 – mux_3_16/XLXI_2 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_58 – add_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_58 – add_16/XLXI_1 – add_8/XLXI_1 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_58 – add_16/XLXI_1 – add_8/XLXI_2 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_58 – add_16/XLXI_3 – add_4
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_5 – alu/XLXI_61 – and_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/CPU – simple_cpu_v1a1/XLXI_8 – control_logic
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/MEMORY – ram_256x16 – ram_256x16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/OUTPUT – reg_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_14 – ram_4Kx16 – ram_4Kx16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_19 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_20 – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_26 – reg_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_10 – reg_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_11 – add_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_15 – mux_2_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_16 – mux_2_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_17 – add_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_18 – lifo_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_29 – mux_3_12
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_30 – data_mux
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_37 – register_file
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_58 – add_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_61 – and_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_62 – mux_4_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_62 – mux_4_16/XLXI_1 – mux_2_16/XLXI_2 – mux_2_8
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_62 – mux_4_16/XLXI_2 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_62 – mux_4_16/XLXI_3 – mux_2_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_5 – alu/XLXI_65 – add_sub_16
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|computer.sch/XLXI_15 – simple_cpu_v1d/XLXI_8 – control_logic
/computer |home|mike|Documents|Test|SimpleCPU_v1d|Src|computer.sch/CPU – simple_cpu_v1d/IR_REG – reg_16
/counter_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|counter_12.sch
/counter_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|counter_16.sch
/counter_8 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|counter_8.sch
/data_mux |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|data_mux.sch
/lifo_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|lifo_12.sch
/mux_2_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_2_12.sch
/mux_2_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_2_16.sch
/mux_2_4 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|mux_2_4.sch
/mux_3_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_3_12.sch
/mux_3_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_3_16.sch
/mux_3_8 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|mux_3_8.sch
/mux_4_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_4_12.sch
/mux_4_16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|mux_4_16.sch
/ram_4Kx16 – ram_4Kx16_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|ram_256x16_syn.vhd
/reg_12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|Src|reg_12.sch
/reg_24 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|reg_24.sch
/register_file |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|register_file.sch
/register_file |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|simple_cpu_v1d|register_file.sch
/register_file_4 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|register_file_4.sch
/register_file_4 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|register_file_4.sch
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/buf12 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|buf12.sch
/buf16 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|buf16.sch
/computer |home|mike|Documents|SYS1_2019|Exam|VLE|SimpleCPU_v1d|Src|computer.sch
/computer |home|mike|Documents|Test|SimpleCPU_v1d|Src|computer.sch/CPU – simple_cpu_v1d
/computer |home|mike|Documents|Test|SimpleCPU_v1d|Src|computer.sch/OUTPUT – reg_8
/computer_tb – behavior |home|mike|Documents|SYS1_2019|Exam|VLE|SimpleCPU_v1d|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers_2|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SYS1|Exam|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SYS1|Exam|VHDL|computer_tb.vhd/uut – computer
/computer_tb – behavior |home|mike|Documents|SYS1|Exam|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d
/computer_tb – behavior |home|mike|Documents|SYS1|Exam|VHDL|computer_tb.vhd/uut – computer/OUTPUT – reg_8
/computer_tb – behavior |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ALU_0 – alu
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/REG_FILE – register_file_4
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/XLXI_48 – buf16
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/XLXI_54 – control_logic
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/MEM – ram_4Kx16 – ram_4Kx16_arch
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|computer_tb.vhd/uut – computer/OUTPUT – reg_8
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ADDR_MUX – mux_3_12
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ALU_0 – alu
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/IR_REG – reg_16
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/PC_CNT – counter_12
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/REG_FILE – register_file
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/XLXI_48 – buf16
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/MEM – ram_4Kx16 – ram_4Kx16_arch
/computer_tb – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/OUTPUT – reg_8
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1_2019|Exam|VLE|SimpleCPU_v1d|cpu_tb.vhd
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers_2|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ADDR_MUX – mux_3_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_0 – alu
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/DATA_BUF – buf16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/IR_REG – reg_16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/PC_CNT – counter_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Exam|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/REG_FILE – register_file_4
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SYS1|Labs|LAB_10_simpleCPU_3|VHDL|VHDL|cpu_tb.vhd
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ADDR_MUX – mux_3_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_0 – alu
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/IR_REG – reg_16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/PC_CNT – counter_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/REG_FILE – register_file_4
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/XLXI_48 – buf16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/XLXI_54 – control_logic
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d1_fpga|VHDL|cpu_tb.vhd/mem – ram_4Kx16 – ram_4Kx16_arch
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ADDR_MUX – mux_3_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_0 – alu
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/ALU_DATA_MUX – data_mux
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/CTL_LOGIC – control_logic
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/IR_REG – reg_16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/PC_CNT – counter_12
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/REG_FILE – register_file
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/cpu – simple_cpu_v1d/XLXI_48 – buf16
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd/mem – ram_4Kx16 – ram_4Kx16_arch
/cpu_testbench – cpu_testbench_arch |home|mike|Documents|Test|SimpleCPU_v1d|cpu_tb.vhd/cpu – simple_cpu_v1d/ADDR_MUX – mux_3_12
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/mem_tb – behavior |home|mike|Documents|SYS1_2019|Labs|LAB_09_simpleCPU_2|VLE|LAB|answers|answers_2|VHDL|mem_tb.vhd
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/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/ALU_0 – alu
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/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/CTL_LOGIC – control_logic
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/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1d/REG_FILE – register_file
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/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/OUTPUT – reg_8
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_26 – reg_16/XLXI_1 – reg_8
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_26 – reg_16/XLXI_2 – reg_8
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_10 – reg_12
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_11 – add_12
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_15 – mux_2_12
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_16 – mux_2_12
/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|computer_tb.vhd/uut – computer/XLXI_15 – simple_cpu_v1d/XLXI_27 – counter_12/XLXI_17 – add_12
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/testbench – behavior |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1d_fpga|VHDL|cpu_tb.vhd
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