— file: clock10MHz_exdes.vhd
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——————————————————————————
— Clocking wizard example design
——————————————————————————
— This example design instantiates the created clocking network, where each
— output clock drives a counter. The high bit of each counter is ported.
——————————————————————————
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock10MHz_exdes is
generic (
TCQ : in time := 100 ps);
port
(– Clock in ports
CLK_IN1 : in std_logic;
— Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
— High bits of counters driven by clocks
COUNT : out std_logic;
— Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clock10MHz_exdes;
architecture xilinx of clock10MHz_exdes is
— Parameters for the counters
———————————
— Counter width
constant C_W : integer := 16;
— When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := ‘0’;
— Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => ‘0’);
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clock10MHz is
port
(– Clock in ports
CLK_IN1 : in std_logic;
— Clock out ports
CLK_OUT1 : out std_logic;
— Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
— Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clock10MHz
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
— Clock out ports
CLK_OUT1 => clk_int,
— Status and control signals
RESET => RESET,
LOCKED => locked_int);
clkout_oddr : ODDR port map
(Q => CLK_OUT(1),
C => clk,
CE => ‘1’,
D1 => ‘1’,
D2 => ‘0’,
R => ‘0’,
S => ‘0’);
— Connect the output clocks to the design
——————————————-
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => ‘0’) after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;