— TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY system_testbench IS
END system_testbench;
ARCHITECTURE behavior OF system_testbench IS
— Component Declaration
COMPONENT simple_cpu_v1a1
PORT(
clk : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector (15 downto 0);
addr : out std_logic_vector (7 downto 0);
data_out : out std_logic_vector (15 downto 0);
ram_en : out std_logic;
ram_wr : out std_logic;
rom_en : out std_logic );
END COMPONENT;
COMPONENT debug
PORT(
clk : in std_logic;
clr : in std_logic;
addr : in std_logic_vector (7 downto 0);
data : in std_logic_vector (15 downto 0) );
END COMPONENT;
COMPONENT ram_256x16_sim
GENERIC (
load_file_name : string := “ram.dat”;
load_file_name_mem : string := “ram.mem”;
load_file_name_coe : string := “ram.coe”;
load_file_name_hex : string := “ram.hex”;
dump_file_name_coe : string := “dump.coe” );
PORT (
clk : in std_logic;
addr_in : in std_logic_vector( 7 downto 0 );
data_in : in std_logic_vector( 15 downto 0 );
data_out : out std_logic_vector( 15 downto 0 );
en : in std_logic;
we : in std_logic;
dump : in std_logic );
END COMPONENT;
SIGNAL VCC, GND : std_logic;
SIGNAL clk : std_logic;
SIGNAL clr : std_logic;
SIGNAL addr : std_logic_vector (7 downto 0);
SIGNAL data_in : std_logic_vector (15 downto 0);
SIGNAL data_out : std_logic_vector (15 downto 0);
SIGNAL ram_en : std_logic;
SIGNAL ram_wr : std_logic;
SIGNAL rom_en : std_logic;
SIGNAL gpo_addr : std_logic;
SIGNAL gpo_en : std_logic;
SIGNAL gpo : std_logic_vector (7 downto 0);
BEGIN
VCC <= '1';
GND <= '0';
gpo_addr <= addr(7) and addr(6) and addr(5) and addr(4) and addr(3) and addr(2) and addr(1) and addr(0);
gpo_en <= gpo_addr and ram_wr;
cpu: simple_cpu_v1a1
PORT MAP(
clk => clk,
clr => clr,
data_in => data_in,
addr => addr,
data_out => data_out,
ram_en => ram_en,
ram_wr => ram_wr,
rom_en => rom_en );
mem : ram_256x16_sim
PORT MAP(
clk => clk,
addr_in => addr,
data_in => data_out,
data_out => data_in,
en => VCC,
we => ram_wr,
dump => GND );
debugger : debug
PORT MAP(
clk => clk,
clr => clr,
data => data_in,
addr => addr );
output : PROCESS( clk, clr )
BEGIN
IF clr = ‘1’
THEN
gpo <= "00000000";
ELSIF clk'event and clk='0'
THEN
IF gpo_en = '1'
THEN
gpo <= data_out(7 downto 0);
END IF;
END IF;
END PROCESS;
clock : PROCESS
BEGIN
clk <= '0';
wait for 50 ns;
clk <= '1';
wait for 50 ns;
END PROCESS clock;
reset : PROCESS
BEGIN
clr <= '1';
wait for 200 ns;
clr <= '0';
wait;
END PROCESS reset;
END;