— Vhdl test bench created from schematic /mnt/hdd/Documents/Web/SimpleCpuDesign/simple_cpu_v1a_fpga/VHDL/simple_cpu_v1d_gpo/subtractor.sch – Tue Oct 8 15:20:37 2019
—
— Notes:
— 1) This testbench template has been automatically generated using types
— std_logic and std_logic_vector for the ports of the unit under test.
— Xilinx recommends that these types always be used for the top-level
— I/O of a design in order to guarantee that the testbench will bind
— correctly to the timing (post-route) simulation model.
— 2) To use this template as your testbench, change the filename to any
— name of your choice with the extension .vhd, and use the “Source->Add”
— menu in Project Navigator to import the testbench. Then
— edit the user defined section below, adding code to generate the
— stimulus for your design.
—
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY subtractor_subtractor_sch_tb IS
END subtractor_subtractor_sch_tb;
ARCHITECTURE behavioral OF subtractor_subtractor_sch_tb IS
COMPONENT subtractor
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
BIN : IN STD_LOGIC;
Difference : OUT STD_LOGIC;
Borrow : OUT STD_LOGIC;
DIFF : OUT STD_LOGIC;
BOUT : OUT STD_LOGIC );
END COMPONENT;
SIGNAL A : STD_LOGIC;
SIGNAL B : STD_LOGIC;
SIGNAL BIN : STD_LOGIC;
SIGNAL Difference : STD_LOGIC;
SIGNAL Borrow : STD_LOGIC;
SIGNAL DIFF : STD_LOGIC;
SIGNAL BOUT : STD_LOGIC;
BEGIN
UUT: subtractor PORT MAP(
A => A,
B => B,
BIN => BIN,
Difference => Difference,
Borrow => Borrow,
DIFF => DIFF,
BOUT => BOUT );
— *** Test Bench – User Defined Section ***
tb : PROCESS
BEGIN
A <= '0'; B <= '0'; BIN <= '0'; WAIT FOR 100 ns;
A <= '0'; B <= '1'; BIN <= '0'; WAIT FOR 100 ns;
A <= '1'; B <= '0'; BIN <= '0'; WAIT FOR 100 ns;
A <= '1'; B <= '1'; BIN <= '0'; WAIT FOR 100 ns;
A <= '0'; B <= '0'; BIN <= '1'; WAIT FOR 100 ns;
A <= '0'; B <= '1'; BIN <= '1'; WAIT FOR 100 ns;
A <= '1'; B <= '0'; BIN <= '1'; WAIT FOR 100 ns;
A <= '1'; B <= '1'; BIN <= '1'; WAIT FOR 100 ns;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;