vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d1_fpga/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SYS1/Exam/VHDL/decoder.sym
vhdtdtfi -lib work decoder.vhd -prj simple_cpu_v1d -o decoder.spl -module decoder -template /opt/Xilinx/14.7/ISE_DS/ISE//data/splfile.tft -deleteonerror
spl2sym -intstyle ise -family zynq -w decoder.spl /home/mike/Documents/SYS1/Exam/VHDL/decoder.sym