— TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_testbench IS
END cpu_testbench;
ARCHITECTURE cpu_testbench_arch OF cpu_testbench IS
— Component Declaration
COMPONENT simple_cpu_v1d
PORT(
CLK : in std_logic;
CLR : in std_logic;
ADDR : out std_logic_vector (11 downto 0);
DATA_IN : in std_logic_vector (15 downto 0);
DATA_OUT : out std_logic_vector (15 downto 0);
ROM_EN : out std_logic;
RAM_EN : out std_logic;
RAM_WR : out std_logic );
END COMPONENT;
COMPONENT ram_4Kx16_sim
PORT (
CLK : in std_logic;
ADDR_IN : in std_logic_vector( 11 downto 0 );
DATA_IN : in std_logic_vector( 15 downto 0 );
DATA_OUT : out std_logic_vector( 15 downto 0 );
EN : in std_logic;
WE : in std_logic;
DUMP : in std_logic );
END COMPONENT;
COMPONENT debug
PORT (
CLK : IN STD_LOGIC ;
CLR : IN STD_LOGIC ;
ADDR : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0) );
END COMPONENT;
SIGNAL VCC : std_logic;
SIGNAL GND : std_logic;
SIGNAL clk : std_logic;
SIGNAL clr : std_logic;
SIGNAL addr : std_logic_vector (11 downto 0);
SIGNAL data_in : std_logic_vector (15 downto 0);
SIGNAL data_out : std_logic_vector (15 downto 0);
SIGNAL rom_en : std_logic;
SIGNAL ram_en : std_logic;
SIGNAL ram_wr : std_logic;
SIGNAL dump : std_logic;
BEGIN
VCC <= '1';
GND <= '0';
dump <= addr(11) and addr(10) and addr(9) and addr(8) and addr(7) and
addr(6) and addr(5) and addr(4) and addr(3) and addr(2) and
addr(1) and addr(0) and ram_en and ram_wr;
-- Component Instantiation
cpu : simple_cpu_v1d PORT MAP(
CLK => clk,
CLR => clr,
ADDR => addr,
DATA_IN => data_in,
DATA_OUT => data_out,
ROM_EN => rom_en,
RAM_EN => ram_en,
RAM_WR => ram_wr );
mem : ram_4Kx16_sim PORT MAP(
CLK => clk,
ADDR_IN => addr,
DATA_IN => data_out,
DATA_OUT => data_in,
EN => VCC,
WE => ram_wr,
DUMP => dump );
disassembler : debug PORT MAP(
CLK => clk,
CLR => clr,
ADDR => addr,
DATA => data_in );
clock : PROCESS
BEGIN
clk <= '0';
wait for 50 ns;
clk <= '1';
wait for 50 ns;
END PROCESS clock;
reset : PROCESS
BEGIN
clr <= '1';
wait for 200 ns;
clr <= '0';
wait;
END PROCESS reset;
END;