— file: clock10MHz.vhd
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——————————————————————————
— User entered comments
——————————————————————————
— None
—
——————————————————————————
— “Output Output Phase Duty Pk-to-Pk Phase”
— “Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)”
——————————————————————————
— CLK_OUT1____10.000______0.000______50.0______467.358____318.001
—
——————————————————————————
— “Input Clock Freq (MHz) Input Jitter (UI)”
——————————————————————————
— __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock10MHz is
port
(– Clock in ports
CLK_IN1 : in std_logic;
— Clock out ports
CLK_OUT1 : out std_logic;
— Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clock10MHz;
architecture xilinx of clock10MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is “clock10MHz,clk_wiz_v3_6,{component_name=clock10MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}”;
— Input clock buffering / unused connectors
signal clkin1 : std_logic;
— Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
— Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
— Dynamic phase shift unused signals
signal psdone_unused : std_logic;
— Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
— Input buffering
————————————–
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
— Clocking primitive
————————————–
— Instantiation of the MMCM primitive
— * Unused inputs are tied off
— * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => “OPTIMIZED”,
CLKOUT4_CASCADE => FALSE,
COMPENSATION => “ZHOLD”,
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 39.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 78.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
— Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
— Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => ‘0’,
— Tied to always select the primary input clock
CLKINSEL => ‘1’,
— Ports for dynamic reconfiguration
DADDR => (others => ‘0’),
DCLK => ‘0’,
DEN => ‘0’,
DI => (others => ‘0’),
DO => do_unused,
DRDY => drdy_unused,
DWE => ‘0’,
— Ports for dynamic phase shift
PSCLK => ‘0’,
PSEN => ‘0’,
PSINCDEC => ‘0’,
PSDONE => psdone_unused,
— Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => ‘0’,
RST => RESET);
— Output buffering
————————————-
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;