— file: clock10MHz_tb.vhd
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——————————————————————————
— Clocking wizard demonstration testbench
——————————————————————————
— This demonstration testbench instantiates the example design for the
— clocking wizard. Input clocks are toggled, which cause the clocking
— network to lock and the counters to increment.
——————————————————————————
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clock10MHz_tb is
end clock10MHz_tb;
architecture test of clock10MHz_tb is
— Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
— timescale is 1ps
constant ONE_NS : time := 1 ns;
— how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
— we’ll be using the period in many locations
constant PER1 : time := 10.000 ns;
— Declare the input clock signals
signal CLK_IN1 : std_logic := ‘1’;
— The high bit of the sampling counter
signal COUNT : std_logic;
— Status and control signals
signal RESET : std_logic := ‘0’;
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := ‘0’;
signal timeout_counter : std_logic_vector (13 downto 0) := (others => ‘0’);
— signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := ‘0’;
signal CLK_OUT : std_logic_vector(1 downto 1);
–Freq Check using the M & D values setting and actual Frequency generated
signal period1 : time := 0 ps;
constant ref_period1_clkin1 : time := (10.000*5*78.000/39.000)*1000 ps;
signal prev_rise1 : time := 0 ps;
component clock10MHz_exdes
port
(– Clock in ports
CLK_IN1 : in std_logic;
— Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
— High bits of counters driven by clocks
COUNT : out std_logic;
— Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
— Input clock generation
————————————–
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simfreqprint(period1, 1);
assert (((period1 - ref_period1_clkin1) >= -100 ps) and ((period1 – ref_period1_clkin1) <= 100 ps)) report "ERROR: Freq of CLK_OUT(1) is not correct" severity note;
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clock10MHz_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
— Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
— High bits of the counters
COUNT => COUNT,
— Status and control signals
RESET => RESET,
LOCKED => LOCKED);
— Freq Check
process(CLK_OUT(1))
begin
if (CLK_OUT(1)’event and CLK_OUT(1) = ‘1’) then
if (prev_rise1 /= 0 ps) then
period1 <= NOW - prev_rise1;
end if;
prev_rise1 <= NOW;
end if;
end process;
end test;