LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mem_tb IS
END mem_tb;
ARCHITECTURE behavior OF mem_tb IS
— Component Declaration for the Unit Under Test (UUT)
COMPONENT ram_4Kx16_sim
PORT(
CLK : IN std_logic;
ADDR_IN : IN std_logic_vector(11 downto 0);
DATA_IN : IN std_logic_vector(15 downto 0);
DATA_OUT : OUT std_logic_vector(15 downto 0);
EN : IN std_logic;
WE : IN std_logic;
DUMP : IN std_logic
);
END COMPONENT;
–Inputs
signal CLK : std_logic := ‘0’;
signal ADDR_IN : std_logic_vector(11 downto 0) := (others => ‘0’);
signal DATA_IN : std_logic_vector(15 downto 0) := (others => ‘0’);
signal EN : std_logic := ‘0’;
signal WE : std_logic := ‘0’;
signal DUMP : std_logic := ‘0’;
–Outputs
signal DATA_OUT : std_logic_vector(15 downto 0);
— Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
— Instantiate the Unit Under Test (UUT)
uut: ram_4Kx16_sim PORT MAP (
CLK => CLK,
ADDR_IN => ADDR_IN,
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
EN => EN,
WE => WE,
DUMP => DUMP
);
— Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
EN <= '1';
ADDR_IN <= "000000000000"; wait for CLK_period*2;
ADDR_IN <= "000000000001"; wait for CLK_period*2;
ADDR_IN <= "000000000010"; wait for CLK_period*2;
ADDR_IN <= "000000000011"; wait for CLK_period*2;
ADDR_IN <= "000000000100"; wait for CLK_period*2;
ADDR_IN <= "000000000101"; wait for CLK_period*2;
wait;
end process;
END;