sch2sym -intstyle ise -family zynq -w -refsym mux_4_16 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/mux_4_16.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/mux_4_16.sym
sch2sym -intstyle ise -family zynq -w -refsym mux_4_16 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/mux_4_16.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/mux_4_16.sym