sch2sym -intstyle ise -family zynq -w -refsym nor_8 /mnt/hdd/Documents/Web/SimpleCpuDesign/simple_cpu_v1a_fpga/VHDL/simple_cpu_v1a/Src/nor_8.sch /mnt/hdd/Documents/Web/SimpleCpuDesign/simple_cpu_v1a_fpga/VHDL/simple_cpu_v1a/nor_8.sym
sch2sym -intstyle ise -family zynq -w -refsym nor_8 /mnt/hdd/Documents/Web/SimpleCpuDesign/simple_cpu_v1a_fpga/VHDL/simple_cpu_v1a/Src/nor_8.sch /mnt/hdd/Documents/Web/SimpleCpuDesign/simple_cpu_v1a_fpga/VHDL/simple_cpu_v1a/nor_8.sym