Quiz14
Due No due date Points 10
Questions 5 Available until Mar 31 at 4:20pm Time Limit 50 Minutes
Instructions
You can take this quiz only once.
Once you start the quiz, you will need to complete it.
This quiz was locked Mar 31 at 4:20pm.
Attempt History
Attempt Time Score
LATEST Attempt 1 18 minutes 4 out of 10
Score for this quiz: 4 out of 10 Submitted Mar 31 at 4:14pm This attempt took 18 minutes.
Question 1
2 / 2 pts
Assume that you have a direct-mapped cache with 16 indexes and each block can contain 16 words. Assuming that an address is 32 bits.
How many bits in each 32bit address are used for its tag?
Correct!
orrect Answers
22
22 (with margin: 0)
16 indexes = 24. So 4 bits are used for indices.
(# of index bits = log 2 (16) = 4)
Also, since each block consists of 16 words, to distinguish 16 words in a block, we need 4 bits (16 = 24) for block offset.
Also, 2 bits are used for Bytes offset.
# of tag bits = 32 – # of index bits – # of block offset bits – # of byte offset bits
= 32 – 4 – 4 – 2 = 22 22 bits for each tag.
Question 2
2 / 2 pts
Assume that you have a direct-mapped cache with 16 indexes and each block can contain 16 words. Assuming that an address is 32 bits.
Compute the total number of bits required to implement this cache.
8,560
8,560 (with margin: 0)
Correct!
orrect Answers
The number of rows = # of indices.
The number of columns = valid bit (1) + (# of tag bits) + (32 x # of words).
Total bits = the number or rows x the number of columns
Total bits = # of indices x (Valid Bit + Tag + Data) = 16 x (1 + 22 + 32 x 16 words)
= 16 x (1 + 22 + 512)
= 16 x 535 = 8560 bits
Question 3
0 / 2 pts
Assume that a cache miss rate (both instruction and data) is 3%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 300 cycles for each miss. Also assume that 36% of instructions are loads and stores. (or the frequency of all loads and stores in a program is 36%.)
a) Assume that I is the instruction count (# of instructions). Compute the total number of cycles for memory stalls.
The total number of cycles for memory stalls ________ x I
12.24 (with margin: 0.5)
ou Answered
orrect Answers
2.4
There are two stages that access the cache/main memory: IF and MEM
IF: Instruction miss cycles = I x 100% x 3% x 300 = 9 x I
MEM: Data miss cycles = I x 36% x 3% x 300 = 3.24 x I
Thus the total number of memory-stall cycles is 9 x I + 3.24 x I = 12.24 x I
Question 4
0 / 2 pts
Assume that a cache miss rate (both instruction and data) is 3%. If a processor has a CPI of 2 without any memory
Y
stalls and the miss penalty is 300 cycles for each miss. Also assume that 36% of instructions are loads and stores. (or the frequency of all loads and stores in a program is 36%.)
b). Compute the effective CPI (considering its cycles for CPU and memory stalls) with this cache.
(Compute the total number of cycles first.)
14.24 (with margin: 0.5)
ou Answered
orrect Answers
2.58
The total number of cycles = 2 (CPI_without_stall) x I + 12.24 x I = 14.24 x I
The effective CPI = the total number of cycles / I (the instruction count)
= (2 x I + 12.24 x I) / I = 14.24
Question 5
0 / 2 pts
Assume that a cache miss rate (both instruction and data) is 3%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 300 cycles for each miss. Also assume that 36% of instructions are loads and stores. (or the frequency of all loads and stores in a program is 36%.)
Y
Determine how much faster a processor would run with a perfect cache that never misses.
i.e., Compute the ratio of the CPU execution time:
7.12 (with margin: 0.9)
ou Answered
orrect Answers
5.44
the ratio of CPU execution time
= CPU time with stalls/ CPU time without any misses
= (I x CPI_stall x Clock cycle) / (I x CPI_no_stall x Clock cycle)
= CPU_stall / CPI_no_stall
(CPI_stall is the answer from the part b.)
The ratio of the CPU execution time = 14.24/2 = 7.12
Quiz Score: 4 out of 10
Y