Based on Garcia’s C61
Single Cycle CPU Control
COMP 273
• •
Summary: A Single Cycle Datapath Rs, Rt, Rd, Imed16 connected to datapath
We have everything except control signals Instruction<31:0>
nPC_sel
Clk
Instruction Fetch Unit
RegDst
Rd Rt 1 Mux 0
RegWr
Rs Rt
ALUctr
Rt Rs Rd Imm16
555 Zero busA
MemWr
0 32 1
MemtoReg
Rw Ra Rb
32 32-bit Registers
busW 32
32 busB0 32
Clk 32 imm16 16 32
1
Data In32 Clk
WrEn Adr Data
Memory
ALUSrc
ExtOp
Based on Garcia’s C61
<0:15> <11:15>
Mux
<16:20> <21:25>
ALU
Mux Extender
An Abstract View of the Critical Path
This affects how much you can overclock your PC!
Critical Path (Load Operation) =
Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, +
ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write
Ideal Instruction Memory
Instruction
5
Instruction Address
Rd Rs Rt Imm 5 5 16
Rw Ra Rb
32 32-bit Registers
32
A 32
B
Data 32 Address
In
Ideal Data Memory
Data
Clk Clk
32
Clk
Based on Garcia’s C61
ALU
PC
Next Address
Recap: Meaning of the Control Signals
• nPC_MUX_sel: “n”=next
• This is the version without jump instructions
4
0 PC <– PC + 4
1 PC <– PC + 4 + {SignExt(Im16) , 00 }
nPC_MUX_sel
Adr 32
Inst Memory
Based on Garcia’s C61
imm16
Clk
00
Adder
PC
Mux
Adder
PC Ext
Instruction Fetch Unit at the End of BRANCH 31 26 21 16 0
• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4
op
rs
rt
immediate
Inst Memory
Adr
nPC_sel
Zero
Instruction<31:0>
• What is meaning of nPC_sel? • Direct MUX select?
• Branch / not branch
• We’ve picked 2nd option, and implemented control logic for BEQ using an AND gate
• How does this need to change for BNE?
• Note: diagram at left shown without jump part of instruction fetch logic circuit
4
nPC_MUX_sel
0 1
Clk
Based on Garcia’s C61
imm16
00
Adder
PC
Mux
Adder
Recap: Meaning of the Control Signals
ExtOp: ALUsrc:
ALUctr:
“zero”, “sign”
0 regB;
1 immed “add”, “sub”, “or”
MemWr: MemtoReg: RegDst: RegWr:
1 write memory 0 ALU; 1 Mem 0 “rt”; 1 “rd” 1 write register
RegDst
Equal
ALUctr MemWr MemtoReg
Rt 10
RegWr
Rd
5 5Rs5Rt
busW
32
Clk
imm16
16
busA
32
busB
32
32
=
0 32 0 32
1 Data In
1
Based on Garcia’s C61
Rw Ra Rb
32 32-bit Registers
Clk
WrEn Adr Data
Memory
ExtOp
ALUSrc
ALU
Mux
Mux
Extender
RTL: The ADD Instruction 31 26 21 16 11 6 0
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
add rd, rs, rt
• MEM[PC]
– Fetch the instruction from memory
• R[rd] = R[rs] + R[rt] – The actual operation
• PC = PC + 4
– Calculate the next instruction’s address
op
rs
rt
rd
shamt
funct
Based on Garcia’s C61
The Single Cycle Datapath during ADD 31 26 21 16 11 6 0
R[rd] = R[rs] + R[rt]
op
rs
rt
rd
shamt
funct
Rs Rt Rd Imm16
Based on Garcia’s C61
1 1 x 0 ADD 0 0 0 0
<0:15> <11:15> <16:20> <21:25>
Single Cycle Datapath during OR Immediate? 31 26 21 16 0
R[rt] = R[rs] OR ZeroExt[Imm16]
op
rs
rt
immediate
Rs Rt Rd Imm16
Based on Garcia’s C61
0 1 0 1 OR 0 0 0 0
<0:15> <11:15> <16:20> <21:25>
The Single Cycle Datapath during LOAD? 31 26 21 16 0
R[rt] = Data Memory {R[rs] + SignExt[imm16]}
op
rs
rt
immediate
Rs Rt Rd Imm16
Based on Garcia’s C61
0 1 1 1 ADD 0 1 0 0
<0:15> <11:15> <16:20> <21:25>
The Single Cycle Datapath during STORE? 31 26 21 16 0
Data Memory {R[rs] + SignExt[imm16]} = R[rt]
op
rs
rt
immediate
Rs Rt Rd Imm16
Based on Garcia’s C61
x 0 1 1 ADD 1 x 0 0
<0:15> <11:15> <16:20> <21:25>
The Single Cycle Datapath during BRANCH 31 26 21 16 0
if (R[rs]-R[rt] == 0) then Zero = 1; else Zero = 0
op
rs
rt
immediate
Rs Rt Rd Imm16
Based on Garcia’s C61
x 0 x 0 SUB 0 x 1 0
<0:15> <11:15> <16:20> <21:25>
The Single Cycle Datapath during JUMP 31 26 25 0
J-type jump
New PC = { PC[31..28], target address, 00 }
op
target address
Based on Garcia’s C61
x0xxx0xx1
Rs Rt Rd Imm16
<0:15> <11:15> <16:20> <21:25>
Step 4: Given Datapath: RTL Control Instruction<31:0>
Inst Memory
Adr
Op Fun
Rt Rs Rd Imm16
Control
nPC_sel
RegWr RegDst ExtOp ALUSrc ALUctr
MemWr
MemtoReg Zero
DATA PATH
Based on Garcia’s C61
<0:15> <11:15>
<16:20> <21:25>
<0:5> <26:31>
A Summary of the Control Signals
See Appendix B
Page 50 onward (or green reference sheet)
func op
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
nPCsel
Jump
ExtOp
ALUctr<3:0>
10 0000
00 0000
add
1
0
0
1
0
0
0
x
Add
10 0010
00 0000
sub
1
0
0
1
0
0
0
x
Subtract
0
1
0
1
0
0
0
0
Or
We Don’t Care !
00 1101 10 0011 10 1011 00 0100 00 0010
ori
lw
0
1
1
1
0
0
0
1
Add
sw
x
1
x
0
1
0
0
1
Add
beq
x
0
x
0
0
1
0
x
Subtract
jump
x
x
x
0
0
x
1
x
x
See 4.4, and Appendix C
R-type I-type J-type
31 26 21 16 11 6 0
op
rs
rt
rd
shamt
funct
add, sub
ori, lw, sw, beq jump
op
rs
rt
immediate
op
target address
Based on Garcia’s C61
Question: Build Control Logic
to implement Jump
Inst31 Inst30 Inst29 Inst28 Inst27 Inst26 Inst25
Jump
Based on Garcia’s C61
Inst01 Inst00
0 0 0 0 1 0
6-input AND
XNOR is 1 when the inputs are the same and 0 when different
Inst31 Inst30 Inst29 Inst28 Inst27 Inst26 Inst25
Control Logic to implement Jump
Jump
Ai
Bi
XNOR
0
0
1
0
1
0
1
0
0
1
1
1
Based on Garcia’s C61
Inst01 Inst00
Based on Garcia’s C61
Question, True or False
1. We should use the main ALU to compute PC=PC+4
2. The ALU is inactive for memory reads or writes.
True, false, or don’t care?
Question
Instruction<31:0>
RegDst
Rd Rt 1 Mux 0
Clk
Rt ALUctr
nPC_sel
RegWr
Rs
Rt Rs Rd
Imm16
MemtoReg
0 1
5 5
Zero
32
Data In 32 Clk
ALUSrc
ExtOp
5 busA
MemWr
busW
32
Clk
32
imm16
16
32
Rw Ra Rb
32 32-bit Registers
busB 0 32
1
32
Instruction Fetch Unit
WrEn Adr
Data Memory
Based on Garcia’s C61
A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?
B. Which of the two signals is not the same (i.e., 1, 0, x) for ADD, LW, SW?
RegDst or ALUctr?
C. “Don’t Care” signals are useful because we can simplify our implementation of the combinatorial Boolean control functions. F / T?
<0:15> <11:15>
Mux
<16:20> <21:25>
ALU
Mux
Extender
And in Conclusion… Single cycle control
• 5 steps to design a processor
1. Analyze instruction set => datapath requirements
2. Select set of datapath components & establish clock methodology
3. Assemble datapath meeting the requirements
4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
5. Assemble the control logic
• Control is the hard part
• MIPS makes that easier
– Instructions same size
– Source registers always in same place
– Immediates same size, location
– Operations always on registers/immediates
Processor
Based on Garcia’s C61
Control
Memory
Input
Datapath
Output
Review and More Information • Textbook Section 4.4
Based on Garcia’s C61