Midterm 1: Virtualiza!on
Due Feb 25 at 9:15pm Points 122 Ques!ons 77
Available Feb 25 at 7:15pm – Feb 25 at 9:15pm about 2 hours Time Limit None Instruc!ons
This exam is open book, open notes. You may use a calculator or a web site (such as h”ps://www.calculator.net/hex-calculator.html that will allow you to convert hexadecimal to decimal and binary and add/subtract hexadecimal numbers.
When you begin the exam, you will need to agree with the following statements:
I understand that this exam must be worked on independently.
During this exam, I may consult personal notes, the OSTEP book, and the lecture slides that were posted on the course web site. I will not communicate or collaborate with any others during the exam in any way; for example:
I will not search for any informa!on on-line (beyond the lecture notes and OSTEP book that have been provided) I will not read or write any on-line shared documents
I will not chat, text, or post any ques!ons or informa!on
I will not ask for, receive, or provide help to others
I will no!fy the instructor if I am aware of others viola!ng this policy.
Unless stated (or implied) otherwise, you should make the following assump!ons:
The OS manages a single uniprocessor (single core) All memory is byte addressable
The terminology lg means log2
210 bytes = 1KB
220 bytes = 1MB
Page table entries require 4 bytes
Data is allocated with op!mal alignment, star!ng at the beginning of a page Leading zeros can be removed from numbers (e.g., 0x06 == 0x6)
Hex numbers are represented with a preceding ¡°0x¡±
You have two hours to complete this exam. The exam will “auto-submit” at the deadline if you have not submi”ed your exam before then.
You will see only one ques!on at a !me and cannot go back and change any answers a#er you have submi”ed them.
You should answer ques!ons as wri”en to the best of your ability; we will not further define terms or explain what is meant by a ques!on. If a True/False statement does not make sense, then it is probably False!
If you have a problem during the exam, please post privately to Instructors Only in Piazza.
To help you pace yourself, we want you to know that this exam is similar in length to the Fall 2019 prac!ce exam; this exam is structured approximately as follows:
)
T/F Ques!ons:
Scheduling: 30 ques!ons, 30 points Virtual Memory: 39 ques!ons, 39 points
Mul!-Part Ques!ons (each sub-ques!on is worth 1 point)
Page Replacement: 11 points (most straight-forward of mul!-part ques!ons) Scheduling: 12 points
Base+Bounds Dynamic Reloca!on: 8 points
TLBs: 14 points
Mul!-level Page Tables (similar to homework): 8 points
Good luck!
This quiz was locked Feb 25 at 9:15pm. A”empt History
A”empt LATEST A”empt 1
Time
118 minutes
Score
84 out of 122
Correct!
Ques!on 1
1 / 1 pts
Before beginning this exam, please read and agree to the following statement:
I understand that this exam must be worked on independently.
During this exam, I may consult personal notes and the lecture slides that were posted on the course web site.
I will not communicate or collaborate with others in any way; for example:
I will not search for any informa!on on-line (beyond the lecture notes that have been provided) I will not read or write any shared documents
I will not chat or post any ques!ons or informa!on
I will not ask for, receive, or provide help to others
I will no!fy the instructor if I am aware of others viola!ng this policy.
At the end of the exam, we will ask you whether or not you followed this policy.
I agree
I do not agree.
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct!
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Ques!on 2
0 / 0 pts
Ques!on 3
1 / 1 pts
Ques!on 4
1 / 1 pts
Ques!on 5
1 / 1 pts
Ques!on 6
1 / 1 pts
Ques!on 7
1 / 1 pts
Ques!on 8
1 / 1 pts
Ques!on 9
0 / 1 pts
Ques!on 10
1 / 1 pts
Ques!on 11
1 / 1 pts
Ques!on 12
0 / 1 pts
Ques!on 13
0 / 1 pts
Ques!on 14
0 / 1 pts
Ques!on 15
1 / 1 pts
Ques!on 16
1 / 1 pts
Ques!on 17
1 / 1 pts
Ques!on 18
1 / 1 pts
Ques!on 19
1 / 1 pts
Ques!on 20
1 / 1 pts
Ques!on 21
1 / 1 pts
Ques!on 22
1 / 1 pts
Ques!on 23
1 / 1 pts
Score for this quiz: 84 out of 122 Submi”ed Feb 25 at 9:12pm
This a”empt took 118 minutes.
True/False: Virtualizing the CPU
You will start with approximately 25-30 ques!ons about virtualizing the CPU. worth 1 point.
Designate if each statement is True or False.
I understand.
Each ques!on is
One of the roles of the OS is to inform applica!ons of the number of other processes they are compe!ng with for each resource.
True False
The values of the stack pointer and program counter (or instruc!on pointer) are part of a process.
True False
A process that is wai!ng to be scheduled on the CPU is in the BLOCKED state.
True False
Each process has its own virtualized registers.
True False
With true mul!-tasking, the user process performs a system call on every !mer interrupt.
True False
With coopera!ve mul!-tasking, the OS can preempt a running process that uses the CPU for a long !me.
True False
Round robin is an example of a scheduling mechanism.
True False
Whenever a !mer interrupt occurs, the OS is responsible for changing the processor privilege mode from user mode to kernel mode.
True False
When execu!ng the return-from-trap instruc!on, the OS restores the (user process’s) registers from the kernel stack, changes to user mode, and jumps to the (user) PC saved on the kernel stack.
True False
The fork() system call creates a copy of the calling process except the PID of the child process will be 0.
True False
The fork() system call creates a child process with an empty heap and stack.
True False
A process is in the ZOMBIE state while its parent process is wai!ng for it to terminate.
True False
Mul!ple processes can be in the BLOCKED state at the same !me.
True False
With a SJF scheduler, processes can suffer from starva!on.
True False
In terms of minimizing average turn-around !me, a STCF scheduler is guaranteed to perform as well or be”er than a SJF scheduler.
True False
RR is more similar to SJF than it is to STCF.
True False
Increasing the length of a RR !me-slice improves average turn-around !me for a workload with jobs of the same length.
True False
A STCF scheduler can suffer from the convoy effect.
True False
Increasing the length of a RR !me-slice tends to increase the number of context-switches.
True False
One reasonable scheduling performance metric is to minimize the number of context switches.
True False
For minimizing average turn-around !me on a workload with jobs of the same length, RR is a be”er choice than FCFS.
True
Correct!
Ques!on 24
1 / 1 pts
Correct!
Ques!on 25
0 / 1 pts
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct Answer You Answered
Correct Answer You Answered
You Answered Correct Answer
Correct Answer You Answered
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct Answer You Answered
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Ques!on 26
1 / 1 pts
Ques!on 27
1 / 1 pts
Ques!on 28
1 / 1 pts
Ques!on 29
1 / 1 pts
Ques!on 30
1 / 1 pts
Ques!on 31
0 / 0 pts
Ques!on 32
1 / 1 pts
Ques!on 33
0 / 1 pts
Ques!on 34
1 / 1 pts
Ques!on 35
0 / 1 pts
Ques!on 36
0 / 1 pts
Ques!on 37
0 / 1 pts
Ques!on 38
0 / 1 pts
Ques!on 39
1 / 1 pts
Ques!on 40
1 / 1 pts
Ques!on 41
0 / 1 pts
Ques!on 42
1 / 1 pts
Ques!on 43
0 / 1 pts
Ques!on 44
1 / 1 pts
Ques!on 45
1 / 1 pts
Ques!on 46
0 / 1 pts
Ques!on 47
1 / 1 pts
Ques!on 48
1 / 1 pts
Ques!on 49
1 / 1 pts
Ques!on 50
1 / 1 pts
Ques!on 51
1 / 1 pts
Correct!
False
RR is a non-preemp!ve scheduling algorithm.
True False
An MLFQ scheduler avoids starva!on by periodically le%ng processes at lower priority levels preempt processes at higher priority levels.
True False
Batch jobs tend to quickly alternate between short CPU bursts and I/O.
True False
With a MLFQ scheduler, a process may preempt another process at the same priority level.
True False
With a MLFQ scheduler, higher priority levels tend to have longer !me-slices than lower priority levels.
True False
One of the goals of an MLFQ scheduler is to enable interac!ve jobs to be scheduled promptly each !me they have a CPU burst.
True False
A MLFQ scheduler requires perfect knowledge of the CPU burst length of each process.
True False
True/False: Virtualizing Memory
Congratula!ons: You have finished the True/False ques!ons about CPU Virtualiza!on.
You will now have approximately 40 ques!ons about how to virtualize memory. Each ques!on is worth 1 point.
Designate if each statement is True or False.
I understand.
Stacks are an efficient organiza!on for memory alloca!on within a virtual address space because stacks do not suffer from fragmenta!on.
True False
With dynamic reloca!on using base+bounds, each user process loads the star!ng loca!on of its address space into the MMU’s base register.
True False
If you use gdb to examine the addresses of global variables in one of your user-level processes, you will see physical addresses.
True False
With sta!c reloca!on, if two different processes write to the same memory address at run-!me, they could read the data that the other process has wri”en.
True False
With the base+bounds approach for dynamic reloca!on, the address space of a process must be allocated con!guously in physical memory.
True False
With dynamic reloca!on, the OS does not need to support system calls.
True False
Given simple segmenta!on, if the stack segment of a process must grow and there is insufficient free space in physical memory adjacent to the stack segment, the OS can move the stack segment in physical memory.
True False
Given simple segmenta!on, with an 18-bit virtual address and 8 possible segments per process, each segment can be a maximum of 8KB.
True False
Given simple segmenta!on, when a user process calls malloc(), the OS may increase the bounds of the heap segment for the currently running process.
True False
Segmenta!on allows user processes to place their code, stack, and heap segments where they choose in physical memory.
True False
Given simple paging, a 32-bit virtual and physical address, and 4KB pages, it is possible for a page to start in physical memory at physical address 0x29ac5200.
True False
With simple linear page tables, when the OS creates a new process with some valid virtual addresses between 0x00000000 and 0xffffffff, the OS must allocate a PTE for every page in that full range.
True False
Given a 16-bit virtual address and 1KB byte pages, there can be up to 64 pages per virtual address space.
True False
If the least-significant 16 bits of a 20-bit physical address are used to designate the offset within a page, then the virtual page size must be 32KB.
True False
With simple linear page tables, given a 32-bit virtual address, 2KB pages, and 8 byte page table entries, each page table could require up to 8MB.
True False
With simple linear page tables, when a user process extends its heap, the OS will allocate space for more PTEs for that process.
True False
On a TLB miss, the OS is likely to perform a context-switch to another process.
True False
A user process that accesses a large array of data using sequen!ally increasing indices (e.g., a[i++]) is likely to have a higher TLB hit rate than one that performs sequen!ally decreasing accesses (e.g., a[i- -]).
True False
A TLB that does not associate an ASID with each TLB entry is likely to have a slightly higher hit rate than a TLB that uses ASIDs.
True False
On a context-switch, the contents of the TLB are typically stored by the OS in the PCB of a process.
True False
Ques!on 52
1 / 1 pts
Correct!
Ques!on 53
0 / 1 pts
Ques!on 54
1 / 1 pts
Ques!on 55
1 / 1 pts
Ques!on 56
1 / 1 pts
Ques!on 57
1 / 1 pts
Ques!on 58
1 / 1 pts
Ques!on 59
0 / 1 pts
Ques!on 60
1 / 1 pts
Ques!on 61
1 / 1 pts
Ques!on 62
0 / 1 pts
Ques!on 63
1 / 1 pts
Ques!on 64
0 / 1 pts
Ques!on 65
1 / 1 pts
Ques!on 66
1 / 1 pts
Ques!on 67
1 / 1 pts
Ques!on 68
1 / 1 pts
Ques!on 69
1 / 1 pts
Ques!on 70
0 / 1 pts
Ques!on 71
0 / 0 pts
Mul!-Part Ques!ons
Congratula!ons: You have finished all of the True/False ques!ons on this exam.
You will now have five mul!-part ques!ons covering different aspects of virtualiza!on.
Most par!al ques!ons require you to type in a numerical value within a box; each of these par!al ques!ons is graded and worth 1 point.
Mul!-Part Ques!ons (each sub-ques!on is worth 1 point)
Page Replacement: 11 points (first topic because it is the most straight-forward of mul!-part ques!ons)
Scheduling: 12 points
Base+Bounds Dynamic Reloca!on: 8 points
TLBs: 14 points
Mul!-level Page Tables: 8 points
I understand
Ques!on 72
7 / 11 pts
Page Replacement Policies (11 sub-ques!ons –> 11 points)
Assume the system contains 3 pages (or frames) of physical memory, each of which is originally empty.
Assume the following access stream of pages: ABCBDADBCDA
Using the OPT page replacement policy and demand paging, indicate whether each page access is a hit, miss, or unknown.
A B C B D
A
D B
C D
A
Other Incorrect Match Op!ons:
Unknown
Miss
Miss
Miss
Hit
Miss
Miss
Correct Answer
Hit
Miss
Correct Answer
Miss
Miss
Correct Answer
Miss
Hit
Hit
Correct Answer
Hit
Hit
10 / 12 pts
If necessary to break !es, assume each scheduler gives preference first to the currently running job (e.g., to minimize context-switches) and second to jobs with names that are earlier alphabe!cally. To answer the ques!ons, you may find it useful to draw the complete Gan” charts.
Enter whole numbers for answers, with no units.
FIFO:
Given a FIFO scheduler, what is the turn-around !me of each job?
8 14 14
16
SJF
Given a SJF scheduler, what is the turn-around !me of each job?
20 6 6
Ques!on 73
CPU Job Scheduling [12 sub-parts –> 12 points]
Assume a workload with the following characteris!cs:
JobName A B C D Arrival Time 0 0 2 4 CPU Burst Length 8 6 2 4
You will compare the performance of FIFO, SJF, and SCTF schedulers for this workload.
Job A:
Job B:
Job C:
Job D:
Job A: Job B: Job C:
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct!
You Answered Correct Answer
Correct!
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered Correct Answer
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered
Correct!
You Answered
Correct!
You Answered
You Answered
One advantage of increasing the size of a page is that a greater por!on of a process’s address space can be reached through the TLB.
True False
With a 3-level page table, 4 memory accesses may be needed to translate a virtual address to a physical address.
True False
With mul!-level page tables, more levels of page tables are likely to be needed if the size of a PTE increases. Assume all other aspects of the virtual address remain the same.
True False
With mul!-level page tables, more levels of page tables are likely to be needed if the size of a page is increased. Assume the number of bits for the virtual address does not change.
True False
Assume a system where segmenta!on and simple paging are combined. When the OS creates a new process with valid virtual addresses of 0x00000000 and 0xffffffff, the OS must allocate a PTE for every page in that full range.
True False
Assume a system with mul!-level page tables. When the OS creates a new process with valid virtual addresses of 0x00000000 and 0xffffffff, the OS must allocate a PTE for every page in that full range.
True False
With a 3-level page table, 0 memory accesses may be needed to translate a virtual address to a physical address.
True False
To avoid accessing page tables, the OS examines each TLB entry to determine if a mapping for the requested VPN is present.
True False
With modern memory/storage hierarchies, lower layers in the hierarchy tend to have greater capacity and be”er performance than higher layers.
True False
Demand paging may have be”er performance than a system with prepaging (or prefetching).
True False
Thrashing can usually be reduced by adding more virtual memory to a system.
True False
FIFO page replacement may have fewer page misses than LRU.
True False
If the dirty bit is set for a physical page, the contents of that page can simply be discarded when that page is evicted.
True False
FIFO page replacement may have fewer page misses than OPT.
True False
If the dirty bit is clear for a physical page, then the contents of the page in physical memory match that of the page on the backing store (e.g., disk).
True False
When a page fault occurs, the OS is likely to context-switch to another user process.
True False
When a page is located on disk and not in memory, its corresponding PTE will have the valid bit cleared.
True False
The OS uses the clock algorithm to find a page in physical memory that has not been accessed recently.
True False
If a TLB miss occurs, the OS must select a vic!m page to replace in physical memory.
True False
Job D:
8
Job D:
8
Correct!
You Answered Correct Answer
You Answered Correct Answer
Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
You Answered Correct Answer
SCTF
Given a SCTF scheduler, what is the turn-around !me of each job?
20 12 2
4
Answer 1:
8
Answer 2:
14
Answer 3:
14
Answer 4:
16
Answer 5:
20
Answer 6:
6
Answer 7:
6
Answer 8:
8
Answer 9:
20
Answer 10:
12 8
Answer 11:
2
Answer 12:
4 8
Job A: Job B: Job C: Job D:
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
You Answered
Correct Answer
Correct!
You Answered
Correct Answer
Ques!on 74
7 / 8 pts
Reverse Engineering for Dynamic Reloca!on
Assume you have an architecture with 64 KB virtual address spaces and 64 KB of physical memory. Assume the system is performing dynamic reloca!on with a base-and-bounds register.
You collect a trace of virtual address to physical address transla!ons and see the following.
Ref #
Virtual address (hex)
Virtual address (decimal)
2596
312
4872
4296
1714
4872
53504
Physical address (hex)
0x1474 0xb88
SEG FAULT 0x1afc 0x24b2 0x3108
0xef00
Physical address (decimal)
5236
2952
SEG FAULT 6908
9394 12552
61184
0 0x0a24
1 0x0138
2 0x1308
3 0x10ac
4 0x06b2
5 0x1308
6 0xd100
Assume the OS does not relocate or change (grow or shrink) any address spaces during this trace. Assume you know that this is a trace of only user-level processes, and that exactly one context- switch occurred. One of your challenges is to determine when this context-switch must have occurred.
Your answers for addresses can be entered in either decimal (e.g., 939) or hex nota!on (e.g., 0x3ab); do not pad your answers with leading zeros (e.g., use 0x3ab and not 0x03ab).
2640
What is value in the base register for the first running process (i.e., process P1)? What is value in the base register for the second running process (i.e., process P2)?
7680
4
For the following transla!ons from virtual to physical addresses:
– if the address transla!on results in a Segmenta!on Fault, enter Seg Fault – if the answer cannot be determined from the info given, type Unknown – if this virtual address could not have been generated, enter Not Possible – otherwise, enter the physical address (in hex or decimal)
For P1, what is the physical address for:
5924 Unknown
Not Possible 6736
Not Possible
What is the first reference number (ref #) when P2 is running?
virtual address 0x0cd4 (3284 decimal)
virtual address 0x1200 (4608 decimal)
virtual address 0x10432 (66610 decimal)
virtual address 0x1000 (4096 decimal) virtual address 0x13c4 (5060 decimal)
Answer 1:
2640 0xa50
Answer 2:
7680 0x1e00
Answer 3:
4
Answer 4:
5924 0x1724
Answer 5:
Unknown
Answer 6:
Not Possible
Answer 7:
6736 0x1a50
Answer 8:
Not Possible Seg Fault
Correct!
Correct Answer
Correct!
Correct Answer
Correct!
Correct!
Correct Answer
Correct!
Correct!
Correct!
Correct Answer
You Answered
Correct Answer
Ques!on 75
1 / 14 pts
TLB Behavior: Determining TLB contents [14 sub-ques!ons –> 14 points]
Assume a system with the following characteris!cs:
– The TLB contains a maximum of 4 entries; the TLB is fully-associa!ve with perfect LRU replacement
– Virtual addresses are 16 bits
– Physical addresses are 20 bits
– Pages are of size 256 bytes
– Instruc!ons are 4 bytes
A user process is execu!ng the following instruc!on stream that con!nues for 512 instruc!ons (the address of the instruc!on is shown in the first column):
0x6000: movl 0x8(%rbp), %edi
0x6004: addl $0x3, %edi
0x6008: movl %edi, 0x8(%rbp)
0x600c: movl 0x8(%rbp), %edi
0x6010: addl $0x3, %edi
0x6014: movl %edi, 0x8(%rbp)
0x6018: movl 0x8(%rbp), %edi
…
3 instructions continue in this pattern as long as needed for question
You will note that the first three instruc!ons are just repeated over and over.
Assume %rip, (the instruc!on pointer register, or PC or program counter) starts at 0x6000. Assume %rbp (the base pointer register) starts at 0x2000.
Reminders:
movl 0x8(%rbp), %edi loads the value at address 0x8 + 0x2000 into the %edi register addl simply adds 3 to the value in the register
movl %edi, 0x8(%rbp) stores the new value in the register back to memory
A#er execu!ng 512 instruc!ons, your goal is to determine the contents of the TLB. Intermediate (graded) ques!ons that may help you with the remainder of this ques!on:
Number of bits in address used for offset:
8 12
4
3 6
8
bits
Maximum number of virtual pages: Maximum number of physical pages:
Number of instruc!ons per page:
Number of pages containing instruc!ons that are accessed:
3
VPN of first instruc!on: VPN of second instruc!on:
(hex) (hex)
VPN of last instruc!on:
VPN of first data access ( 0x8(%rbp)):
VPN of last data access ( 0x8(%rbp)):
0x2000
0x2004 0x2008
(hex)
(hex)
(hex)
A#er we execute 512 instruc!ons, which four VPNs will be in the TLB?
Order your four answers from lowest VPN to highest VPN. Assume the TLB begins with four INVALID entries. Specify your answers in hex nota!on (i.e., 0x…).
If the VPN of a TLB entry is unknown, enter UNKNOWN If a TLB entry remains INVALID, enter INVALID
VPN in TLB entry:
VPN in TLB entry:
VPN in TLB entry:
UNKNOWN UNKNOWN UNKNOWN UNKNOWN
(hex) (hex) (hex) (hex)
VPN in TLB entry:
Note: You do not know anything about the corresponding PPNs for these TLB entries.
Answer 1:
8
Answer 2:
8 256
Answer 3:
12
4096
4K
Answer 4:
4 64
Answer 5:
3 8
Answer 6:
0x2000 0x60
Answer 7:
0x2004 0x60
Answer 8:
0x2008 0x67
Answer 9:
3 0x20
Answer 10:
6 0x20
Answer 11:
UNKNOWN 0x20
Answer 12:
UNKNOWN 0x65
Answer 13:
UNKNOWN 0x66
Answer 14:
UNKNOWN 0x67
Ques!on 76
Mul!-Level Page Tables [8 sub-ques!ons –> 8 points]
This ques!on has the same setup as your homework.
Assume dynamic reloca!on is performed with a two-level page table with no TLB.
8 / 8 pts
Assume the page size is 32 bytes, the virtual address space for the current process is 1024 pages, or 32 KB, and physical memory consists of 128 pages.
A virtual address needs 15 bits (5 for the offset, 10 for the VPN) and a physical address 12 bits (5 offset, 7 for the PFN). The upper five bits of a virtual address index into a page directory; the page directory entry (PDE), if valid, points to a page of the page table.
Each page table holds 32 page-table entries (PTEs). Each PTE, if valid, holds the desired transla!on (physical frame number, or PFN) for the virtual page. The format of an 8-bit PTE is VALID | PFN6 … PFN0.
PDBR: 0xd (13)
Contents of memory are as follows:
Consider an access to virtual address 0x6dd9 and the necessary memory accesses in order to perform the address transla!on.
Enter all results in hexadecimal without unnecessary leading zeros (e.g., 0xa not 0x0a). If an access is not valid, will not occur, or leads to an error, enter Error
What is the first page accessed?
What is the offset on the first page?
What contents (i.e., value) will be read on the first access?
0xd (hex) 0x1B (hex)
What is the second page accessed?
0xC7 0x47 (hex)
(hex)
(hex) (hex)
0x16
What is the offset on the second page?
0xE (hex) 0xA8
What contents (i.e., value) will be read on the second access?
What is the corresponding final physical address?
What contents (i.e., value) will be read from the final physical address?
Answer 1:
0xd
Answer 2:
0x1b
Answer 3:
0xc7
Answer 4:
0x47
Answer 5:
0xe
Answer 6:
0xa8
Answer 7:
0x519
Answer 8:
0x16
(hex)
0x519
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Correct!
Ques!on 77
1 / 1 pts
Congratula!ons, you completed the CS 537 Midterm!
Please a”est that you did not communicate or collaborate with others during the exam in any way; for example:
I did not search for any informa!on on-line (beyond the lecture notes that have been provided) I did not read or write any shared documents
I did not test, chat, or post any ques!ons or informa!on
I did not ask for, receive, or provide help to others
I will no!fy the instructor if I am aware of others viola!ng this policy.
I agree
I do not agree
Correct!