CS计算机代考程序代写 cache 1.False sharing vs. True sharing

1.False sharing vs. True sharing
https://software.intel.com/content/www/us/en/ develop/articles/avoiding-and-identifying-false- sharing-among-threads.html
True sharing: true sharing, would require programmatic synchronization constructs to ensure ordered data access.
False sharing: The frequent coordination required between processors when cache lines are marked ¡®Invalid¡¯ requires cache lines to be written to memory and subsequently loaded. False sharing increases this coordination and can significantly degrade application performance.

Example 1 (quiz 2)
Consider the program below, is there any potential performance issue with it? If there is, how to
fix it? Note that the two functions are concurrently executed on two different processor cores,
each of which has its own cache hierarchy.
Is there false sharing? Is there true sharing?
Example 2 (Intel Tutorial Link)

Is there false sharing? True sharing? How to avoid it?
In summary, what are the typical ways to resolve false sharing? And what are the typical ways to resolve true sharing caused race condition issues?
2.What causes a race condition and requires mutual exclusive?
Example 3 (quiz 2)
Please consider the following program. The program’s original intention was to print -out ¡°hello
from thread 0¡±, ‘hello from thread 1’ all the way to ‘hello from thread 9’ (note that the order of the
printout should be random). However, there are several bugs in the code below. Please list all the bugs appeared in this code and explain why they cause problems. Please provide a fix to the code so it can run correctly.