CS3350B Computer Organization Introduction
Alex Brandt
Department of Computer Science University of Western Ontario, Canada
Monday January 11, 2021
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Outline
1 Highlights of Hardware History
2 Modern Computer Architectures
3 System and Hardware Abstractions
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Konrad Zuse’s Z3 electro-mechanical computer (1941, Germany). Turing complete, though conditional jumps were missing.
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Colossus (1941, UK) was the world’s first totally electronic programmable computing device. But not Turing complete.
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Harvard Mark I – IBM ASCC (1944, US). Electro-mechanical computer. No conditional jumps and not Turing complete. It could store 72 numbers, each 23 decimal digits long. It could do three additions or subtractions in a second. A multiplication took six seconds, a division took 15.3 seconds, and a logarithm or a trigonometric function took over one minute.
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Electronic Numerical Integrator And Computer (ENIAC, 1945). The first general-purpose, electronic computer. It was a Turing-complete, digital computer capable of being reprogrammed and was running at 5,000 cycles per second for operations on the 10-digit numbers.
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The IBM Personal Computer (IBM PC) (Introduced on August 12, 1981).
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Outline
1 Highlights of Hardware History
2 Modern Computer Architectures
3 System and Hardware Abstractions
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Von Neumann Architecture
The Von Neumann architecture saw a shared memory for instructions and data. Modern computers, especially w.r.t what software “sees”, use his model.
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Harvard Architecture
The Harvard architecture has separated memory banks and channels for instructions and data.
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Multi-core Architecture
Core
Core
Core
Core
L1 inst
L1 data
L1 ins
L1 data
L1 ins
L1 data
L1 ins
L1 data
L2
L2
Main Memory
Modern multi-core processors see a varying hierarchy of independent and shared memories.
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Memory Hierarchy
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Cache Memory Statistics
Size
Size
32 KB
Size
6 MB
L1 Data Cache
Line Size
L1 Instruction Cache
Line Size
64 bytes
Line Size
64 bytes
Latency
Latency
3 cycles
Latency
14 cycles
Associativty
8‐way
Associativty
8‐way
L2 Cache
Associativty
24‐way
32 KB 64 bytes 3 cycles
Typical cache specifications of a multicore in 2008.
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The Processor-Memory Gap is a key contributor to the Memory Wall – the point where a program’s performance is totally determined by memory speed. Faster processors will not make programs run faster!
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Outline
1 Highlights of Hardware History
2 Modern Computer Architectures
3 System and Hardware Abstractions
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Components of a computer
Same components for all kinds of computer ë desktop, server, supercomputer, embedded
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Layers of Software
Application software
ë Written in a high-level language (HLL) ë Javascript, Python, Java.
System software
ë Compiler: translates HLL code to machine code
ë Operating system: service code Handling input/output
Managing memory and storage Scheduling tasks & sharing resources
Hardware
ë Processor, memory, I/O controllers
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Levels of Program Code
High-level language
ë Level of abstraction closer to problem domain
ë Provides productivity and portability
Assembly language
ë Textual representation of machine instructions
Hardware representation
ë Binary encoding of instructions and data
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Layers of Abstraction in Computer Systems
After a brief look at processors and memory, we will start down at circuit design and build up to ISA.
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Complicated Systems are Inevitable
Think economic specialization.
Each layer is separate and can be optimized independently in the pursuit of performance.
Eight great ideas in computer architecture (Patterson)
1 Use abstraction to simplify design
2 Design for Moore’s Law
3 Make the common case fast
4 Performance via parallelism
5 Performance via pipelining
6 Performance via prediction
7 Hierarchy of memories
8 Dependability via redundancy
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Great Idea #1: Abstraction
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $t0, 0($2)
lw $t1, 4($2)
sw $t1, 0($2)
sw $t0, 4($2)
# Anything can be represented as a
# number, i.e., data or instructions 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
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Great idea #2: Design for Moore’s Law
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Great idea #4: Performance via Parallelism
Parallelism can be used to tackle the processor-memory gap.
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Great idea #5: Performance via Pipelining
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Great idea #7: Memory Hierarchy (Principle of Locality)
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Great Idea #8: Dependability via Redundancy
Redundancy so that a failing piece doesn’t make the whole system fail
Increasing transistor density reduces the cost of redundancy
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Great Idea #8: Dependability via Redundancy
Applies to everything from physical hardware components to the data encoded in binary.
Redundant data centers so that can lose 1 datacenter but Internet service stays online
Redundant disks so that can lose 1 disk but not lose data (Redundant Arrays of Independent Disks/RAID)
Redundant memory bits of so that can lose 1 bit but no data (Error Correcting Code/ECC Memory)
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In This Course…
Check the syllabus!
Course topics
Evaluation
Schedule
Textbook (recommended, not required) Missed quiz policies
TAs, Office hours
Check OWL for continued updates and announcements. It’s your fault if you miss something that was announced.
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Acknowledgements
The lecture slides of this course are adapted from previous years’ slides by Marc Moreno Maza which in turn have been adapted from text book accompaniments and teaching materials posted on the internet by other Computer Architecture instructors.
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