COMP 30080 Computer Systems
2. MIPS Instructions: The Language of the Computer
Assoc. Prof.
UCD School of Computer Science. Scoil na Ríomheolaíochta UCD.
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Introduction
1. Recap: von Neumann architecture
2. Fetch-decode-execute cycle
3. About MIPS
4. MIPS Assembly Language and MARS simulator 5. Worked out exampe
von Neumann architecture
Main Memory
address data
instruction
PC Control Unit
MIPS32: 32-bit words in memory
32 data registers, each storing a 32-bit word
RISC versus CISC
• “A Reduced Instruction Set Computer (RISC) is designed to perform a small set of simple machine instructions at high speed.” e.g. MIPS, ARM.
• “A Complex Instruction Set Computer (CISC) is designed to perform a large set of compound machine instructions, each consisting of several operations.” e.g. Intel x86-64 ISA.
• CISC instructions tend to be more programmer-friendly and result in slightly shorter programs, but require more CPU hardware to implement than RISC instructions.
• RISC instructions tend to be more compiler friendly and require less CPU hardware to implement than CISC instructions.
MIPS (Microprocessor without Interlocked Pipeline Stages)
• 1981 at Stanford started work on RISC (Reduced Instruction Set Computer) with deep pipeline
• 1984 he set up MIPS Computer Systems
• 1985 MIPS created R2000, 32-bit RISC microprocessor
• 1991 MIPS created R4000, 1st 64-bit microprocessor
• 1992 MIPS was acquired by their main customer SGI (graphics workstations), to become MIPS Technologies
• 1990s MIPS licensed processors for embedded systems
• 2012-2018 MIPS Technologies changes ownership several times
• 2018-2019 Short-lived attempt at open-sourcing of MIPS ISA.
https://www.mips.com/mipsopen/
. Hennessy
• Stanford President . First International Advisor to Trinity College Dublin / University College Dublin Innovation Alliance
Stanford President Dr . Hennessy, Taoiseach Brian Cowen, TCD Provost Dr John Hegarty and UCD President Dr Hugh Brady.
• Why MIPS for this course?
– ‘Clean’ ISA – logical, few special cases
– Comparatively easy to understand
– Good texts
– Tool support
– Principals learnt are applicable to other architectures
– Even classic CISC architectures such as IA-32 now use RISC concepts internally in the processors
• Nowadays two ISA variants MIPS-32 and MIPS-64
this course
MIPS Assembly Language and MARS simulator
Arithmetic Instructions
a = b + c;
C equivalent 3 variables
MIPS instruction
Register map
add $s0, $s1, $s2 # data in registers
operands – register names
MUST HAVE 3 AND ONLY 3 OPERANDS
Arithmetic Instructions
d = b – c;
sub $s3, $s1, $s2 # data in registers
• How to deal with more than three variables?
f = (g + h) – (i + j);
add $t0, $s1, $s2 # $t0 contains g + h
add $t1, $s3, $s4 # $t1 contains i + j
sub $s0, $t0, $t1 # $s0 contains result
Arithmetic Instructions
a = a + 4;
addi $s3, $s3, 4
add immediate
destination source
Arithmetic Instructions
a = a – 2;
addi $s3, $s3, -2
Core Arithmetic Instructions
Instruction
MIPS Example
C Equivalent
add $t0,$t1,$t2
t0 = t1 + t2
Add immediate
addi $t0,$t1,2
t0 = t1 + 2
sub $t0,$t1,$t2
t0 = t1 – t2
Core Logical Instructions
Instruction
MIPS Example
C Equivalent
Bitwise AND
and $s1,$s2,$s3
s1 = s2 & s3
Bitwise OR
or $s1,$s2,$s3
s1 = s2 | s3
Bitwise NOR
nor $s1,$s2,$s3
s1 = ~(s2 | s3)
Bitwise AND with constant
andi $s1,$s2,100
s1 = s2 & 100
Bitwise OR with constant
ori $s1,$s2,100
s1 = s2 | 100
Shift left logical by constant
sll $s1,$s2,10
s1 = s2 << 10
Shift right logical by constant (zeros are shifted in on the left)
srl $s1,$s2,10
s1 = s2 >>> 10
Shift right arithmetic by constant (sign bit is shifted in on the left)
sra $s1,$s2,10
s1 = s2 >> 10
• Set a Boolean to indicate if variable a is odd (TRUE) or not (FALSE).
lw $t1, 0($t0)
andi $t2, $t1, 1
Bit shifting for quick multiplication or division by 2n
• Bit shifting can be used as a quick way to multiply or divide an integer by 2k where k is the number of bits it is shifted by.
• Number x with n binary digits bnbn-1…b1b0 has value x=2nbn +2n-1bn-1+…+21b1+20b0
• Suppose that we shift x to the left by 1 bit: y = x << 1
• The new number y has n+1 binary digits bnbn-1...b1b00 and has value
y=2n+1bn +2nbn-1+...+22b1+21b0+0= 2(2nbn +2n-1bn-1+...+21b1+20b0)=2x
• It is easy to prove that
x << n = 2nx and x >> n = x / 2n
• What is the value of $t3 after performing the following instructions?
addi $t1, $t0, 2
sll $t2, $t1, 2
$t2 = 22(1+2) = 4(1+2)= 12
Memory Instructions
g = h + a[2];
destination load word
offset of element (in bytes) relative to base
register containing base address of array a
# load a[2] to $t0 #g=h+a[2]
lw $t0, 8($s3) add $s1,$s2,$t0
actual address = base + offset
Memory Instructions
a[12] = h + a[8];
lw $t0, 32($s3) # load a[8] add $t0, $s2, $t0 # calculate
sw $t0, 48($s3) # store result
store word
Address of / pointer to
source destination
• Implement the following in MIPS32 assembly language
y = x[1]+2;
lw $t2, 4($t1)
addi $t0, $t2, 2
• Implement the following in MIPS32 assembly language:
y = x[i] + a;
sll $t2, $s0, 2
add $t3, $t1, $t2
lw $t4, 0($t3)
lw $t5, 0($t0)
add $t6, $t4, $t5
Flow Control
jump (unconditional)
… L1: …
jump destination
label, assembler puts in actual address of destination instruction
destination instruction
Flow Control
beq $s3, $s4, L2
VERY, VERY IMPORTANT!!
… L2: …
branch if equal, otherwise continue
jump destination
if (a == b)
Flow Control
if (a != b)
… L3: …
bne $s3, $s4, L3
# branch destination
branch if not equal
if (a == b)
f = g + h;
f = g – h;
bne $s3, $s4, Else # TEST ELSE!!! add $s0,$s1,$s2 #thenf=g+h j IfEnd
Else: sub $s0,$s1,$s2 #elsef=g–h IfEnd:
if (a == b)
f = g + h;
f = g – h;
beq $s3, $s4, Then # TEST THEN
sub $s0,$s1,$s2 #thenf=g+h j IfEnd
Then: add $s0,$s1,$s2 #elsef=g–h IfEnd:
• Consider the common types of loops:
for (i=0; i
addi $t0, $zero, 8 Loop: body
addi $t0, $t0, -1 bne $t0, $zero, Loop
# i not used in body
index decrement
while (x == 3) {
pre-test continuation condition
Loop: Exit: …
termination condition
addi $t1, $zero, 3 bne $t0, $t1, Exit body
} while (x == 3)
addi $t1, $zero, 3 Loop: body
beq $t0, $t1, Loop
} until (x == 3)
post-test termination condition
addi $t1, $zero, 3 Loop: body
bne $t0, $t1, Loop
continuation condition
while (b[i] == k)
i = i + 1;
Loop: sll $t1,$s3,2 add $t1, $t1, $s6
#$t1=i*4 # $t1 = *b[i] # $t0 = b[i] #
# repeat loop
lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3,$s3,+1
Execution Time
• On simple processors, the execution time of a program is directly proportional to the number of instructions executed.
• How could the execution time of the pop quiz solution be reduced?
add $t1, lw $t0, bne $t0, addi $t1, j Loop
$s5, Exit # jump out if not equal
sll $t1,$s3,2
# $t1 = address of b[i] # $t0 = b[i]
Exit: sub $t1,
srl $t3, $t1, 2
# current address =+ 4
# repeat loop
# re-calculate i
Complex Conditions
if ( (a==0) && (b==0) ) {
bne $t1,$zero,SkipBody bne $t2,$zero,SkipBody body
do condition
SkipBody: …
skip condition
Complex Conditions
if ( (a==0) || (b==0) ) {
beq $t1, $zero, DoBody
beq $t2, $zero, DoBody
j Skip
DoBody: body Skip: …
Core Branch and Jump Instructions
Instruction
MIPS Example
C Equivalent
Branch on equal
beq $s1,$s2,Label
if (s1 == s2)
goto Label
Branch on not equal
bne $s1,$s2,Label
if (s1 != s2)
goto Label
goto Label
Jump register
Jump and link
• Handy feature:
$zero is a special register whose value is fixed to zero.
Let’s explore some examples
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