CS计算机代考程序代写 mips compiler computer architecture assembler Digital System Design 4 Lecture 6 – Instruction Sets 1

Digital System Design 4 Lecture 6 – Instruction Sets 1
Computer Architecture Chang Liu

Course Outline
Week
Lecture
Topic
Chapter
Tutorial
1
1
Introduction
1
2
A Historical Perspective
2
3
Modern Technology and Types of Computer
2
4
Computer Perfomance
1
3
5
Digital Logic Review
C
3
6
Instruction Set Architecture 1
2
4
7
Instruction Set Architecture 2
2
4
8
Processor Architecture 1
4
5
9
Instruction Set Architecture 3
2
5
10
Processor Architecture 2
4
Festival of Creative Learning
6
11
Processor Architecture 3
4
6
12
Processor Architecture 4
Instruction Sets 1 – Chang Liu
4
2

L5 Summary: Hardware is Plumbing
Software
ISA
Hardware
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This Lecture
• Introduction to Instruction Sets • Basic Operands
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The Big Picture
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Questions
How do the software and the hardware interface with one another?
What width are each of these bus lines? What happens, physically, when bus lines connect or divide?
How many instructions can you hold in the instruction memory? How many registers are there?
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Instruction Set
• The repertoire of instructions of a computer
• Different computers have different instruction sets
– But with many aspects in common
• Early computers had very simple instruction
sets
– Simplified implementation
• Many modern computers also have simple instruction sets
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1. 2.
Two Key Principles of Machine Design
Instructions are represented as numbers and, as such, are indistinguishable from data
Programs are stored in alterable memory (that can be read
or written to) just like data
Stored-program concept
• Programs can be shipped as files of binary numbers – binary compatibility
• Computers can inherit ready- made software provided they are compatible with an existing ISA – leads industry to align around a small number of ISAs
Memory
Accounting prg (machine code)
C compiler (machine code)
Payroll data
Source code in C for Acct prg

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8
Irwin, PSU, 2008

The MIPS Instruction Set
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MIPS-32 ISA • Instruction Categories
– Computational
– Load/Store
– Jump and Branch
– Floating Point • coprocessor
– Memory Management – Special
3 Instruction Formats: all 32 bits wide
Registers
R0 – R31
PC
HI
op
rs
rt
rd
sa
funct
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10
LO
R format I format
J format
op
rs
rt
immediate
op
jump target

1.
MIPS (RISC) Design Principles
Simplicity favors regularity
– fixed size instructions
– small number of instruction formats
– opcode always the first 6 bits
Smaller is faster
– limited instruction set
– limited number of registers in register file
– limited number of addressing modes
Make the common case fast
– arithmetic operands from the register file (load-store machine)
– allow instructions to contain immediate operands
Good design demands good compromises
– three instruction formats
2.
3. 4.
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Arithmetic Operations • Add and subtract, three operands
– Two sources and one destination adda,b,c #agetsb+c
• All arithmetic operations have this form
• Design Principle 1: Simplicity favours regularity
– Regularity makes implementation simpler
– Simplicity enables higher performance at lower cost
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Arithmetic Example • C code:
f = (g + h) – (i + j);
• Compiled MIPS code:
add t0, g, h
add t1, i, j
sub f, t0, t1
# temp t0 = g + h
# temp t1 = i + j
# f = t0 – t1
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Register Operands
• Arithmetic instructions use register operands
• MIPS has a 32 × 32-bit register file – Use for frequently accessed data
– Numbered 0 to 31
– 32-bit data called a “word”
• Assembler names
– $t0, $t1, …, $t9 for temporary values – $s0, $s1, …, $s7 for saved variables
• Design Principle 2: Smaller is faster – c.f. main memory: millions of locations
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Register Operand Example
• C code:
f = (g + h) – (i + j);
– f, …, j in $s0, …, $s4
• Compiled MIPS code:
add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1
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Memory Operands
• Main memory used for composite data
– Arrays, structures, dynamic data
• To apply arithmetic operations
– Load values from memory into registers – Store result from register to memory
• Memory is byte addressed
– Each address identifies an 8-bit byte
• Words are aligned in memory – Address must be a multiple of 4
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Memory Operand Example 1
• C code:
g = h + A[8];
– g in $s1, h in $s2, base address of A in $s3 • Compiled MIPS code:
– Index 8 requires offset of 32 • 4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0
offset
base register
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Memory Operand Example 2
• C code:
A[12] = h + A[8];
– h in $s2, base address of A in $s3
• Compiled MIPS code:
– Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word
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Registers vs. Memory
• Registers are faster to access than memory
• Operating on memory data requires loads and stores
– MIPS is a Load-Store Architecture – More instructions to be executed
• Compiler must use registers for variables as much as possible
– Only spill to memory for less frequently used variables
– Register optimization is important!
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Immediate Operands
• Constant data specified in an instruction
addi $s3, $s3, 4
• No subtract immediate instruction – Just use a negative constant
addi $s2, $s1, -1
• Design Principle 3: Make the common case fast
– Small constants are common
– Immediate operand avoids a load instruction
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The Constant Zero
• MIPS register 0 ($zero) is the constant 0
– Cannot be overwritten
• Useful for common operations – E.g., move between registers
add $t2, $s1, $zero
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Unsigned Binary Integers • Given an n-bit number
n1 n2 1 0 xxn12 xn22 x12 x02
• Range: 0 to +2n – 1 • Example
– 0000 0000 0000 0000 0000 0000 0000 10112 = 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
• Using 32 bits
– 0 to +4,294,967,295
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2s-Complement Signed Integers • Given an n-bit number
n1 n2 1 0 xxn12 xn22 x12 x02
• Range: –2n – 1 to +2n – 1 – 1 • Example
– 1111 1111 1111 1111 1111 1111 1111 11002 = –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
• Using 32 bits
–2,147,483,648 to +2,147,483,647
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Sign Extension
• Representing a number using more bits
– Preserve the numeric value
• In MIPS instruction set
– addi: extend immediate value
– lb, lh: extend loaded byte/halfword – beq, bne: extend the displacement
• Replicate the sign bit to the left – c.f. unsigned values: extend with 0s
• Examples: 8-bit to 16-bit
– +2: 0000 0010 => 0000 0000 0000 0010 – –2: 1111 1110 => 1111 1111 1111 1110
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Next Lecture •Representing Instructions in the Computer
–R Format & I Format •Instructions for making decisions
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