Digital System Design 4 Lecture 12 – Processor Architecture 4
Computer Architecture Dr Chang Liu
Course Outline
Week
Lecture
Topic
Chapter
Tutorial
1
1
Introduction
1
2
A Historical Perspective
2
3
Modern Technology and Types of Computer
2
4
Computer Perfomance
1
3
5
Digital Logic Review
C
3
6
Instruction Set Architecture 1
2
4
7
Instruction Set Architecture 2
2
4
8
Processor Architecture 1
4
59
Instruction Set Architecture 3 2
5
10
Processor Architecture 2
4
Festival of Creative Learning
6
11
Processor Architecture 3
4
6
12
Processor Architecture 4
Processor Architecture 4 – Chang Liu
4
This Lecture • Pipelined Datapath
• Pipeline Control
Processor Architecture 4 – Chang Liu
MIPS Pipeline
Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register
Processor Architecture 4 – Chang Liu
MIPS Pipelined Datapath
MEM
Right-to-left flow leads to hazards
WB
Processor Architecture 4 – Chang Liu
Pipeline registers • Need registers between stages
– To hold information produced in previous cycle
Processor Architecture 4 – Chang Liu
Pipeline Operation
• Cycle-by-cycle flow of instructions through the pipelined datapath
– “Single-clock-cycle” pipeline diagram • Shows pipeline usage in a single cycle
• Highlight resources used
– c.f. “multi-clock-cycle” diagram • Graph of operation over time
• We’ll look at “single-clock-cycle” diagrams for load & store
Processor Architecture 4 – Chang Liu
IF for Load, Store, …
Processor Architecture 4 – Chang Liu
ID for Load, Store, …
Processor Architecture 4 – Chang Liu
EX for Load
Processor Architecture 4 – Chang Liu
MEM for Load
Processor Architecture 4 – Chang Liu
WB for Load
Wrong register number
Processor Architecture 4 – Chang Liu
Corrected Datapath for Load
Processor Architecture 4 – Chang Liu
EX for Store
Processor Architecture 4 – Chang Liu
MEM for Store
Processor Architecture 4 – Chang Liu
WB for Store
Processor Architecture 4 – Chang Liu
Multi-Cycle Pipeline Diagram • Form showing resource usage
Processor Architecture 4 – Chang Liu
Single-Cycle Pipeline Diagram • State of pipeline in a given cycle
Processor Architecture 4 – Chang Liu
Pipelined Control
Processor Architecture 4 – Chang Liu
Pipelined Control
• Control signals derived from instruction
– As in single-cycle implementation
Processor Architecture 4 – Chang Liu
Pipelined Control
Processor Architecture 4 – Chang Liu
Pipeline Summary
• Pipelining improves performance by increasing instruction throughput
– Executes multiple instructions in parallel – Each instruction has the same latency
• Subject to hazards
– Structure, data, control
• Pipeline registers: data + control Processor Architecture 4 – Chang Liu
Next Lecture
• Dr Smith
• Memory Access Locality • Caches
• Memory Hierarchy
• Week 11, a revision lecture by Chang Liu Processor Architecture 4 – Chang Liu