Digital System Design 4 Lecture 10 – Processor Architecture 2
Computer Architecture Dr Chang Liu
Course Outline
Week
Lecture
Topic
Chapter
Tutorial
1
1
Introduction
1
2
A Historical Perspective
2
3
Modern Technology and Types of Computer
2
4
Computer Perfomance
1
3
5
Digital Logic Review
C
3
6
Instruction Set Architecture 1
2
4
7
Instruction Set Architecture 2
2
4
8
Processor Architecture 1
4
59
Instruction Set Architecture 3 2
5
10
Processor Architecture 2
4
Festival of Creative Learning
6
11
Processor Architecture 3
4
6
12
Processor Architecture 4
Processor Architecture 2 – Chang Liu
4
2
This Lecture
• Branch datapath
• Main control unit
• ALU control
• Build up datapath with control
Processor Architecture 2 – Chang Liu 3
Reminder of Branch Instructions
3 Instruction Formats: all 32 bits wide
op
rs
rt
rd
sa
funct
R format I format
J format
op
rs
rt
immediate
op
jump target
• Instructions that branch
– beq, bne e.g. $s1, $s2, 25
– j e.g. j 2500
Processor Architecture 2 – Chang Liu
4
Branch Instructions • Read register operands
• Compare operands
– Use ALU, subtract and check Zero output
• Calculate target address
– Sign-extend displacement
– Shift left 2 places (word displacement)
– Add to PC + 4
• Already calculated by instruction fetch
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Branch Instructions
Just re-routes wires
Sign-bit wire replicated
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Full Datapath (without control)
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•
Building it Up: Controller
If we are clever, we can design the instructions so that we extract bits from the instructions and use these as the controls signals
– Actually: have to do this in stages
– Pull out some bits (Opcode), use this as control for a MUX which
chooses other instruction bits to become the controls…
‘Micro-code’ processors have (effectively) another processor in here to control the control signals (!)
– The code for this control signal generating processor is called micro-code and is stored in protected firmware on the CPU
– Means CPU can be ‘reprogrammed’ to handle new instructions
– Could be used for emulation (but isn’t)…
•
Processor Architecture 2 – Chang Liu 8
The Main Control Unit
• Control signals derived from instruction
0
rs
rt
rd
shamt
funct
R-type
Load/ Store
Branch
31:26
31:26
31:26
opcode
25:21
25:21
25:21
20:16
20:16
20:16
15:11
10:6 5:0
15:0
15:0
35 or 43
rs
rt
address
4
rs
rt
address
always read
read, except for load
Processor Architecture 2 – Chang Liu
9
write for R-type and load
sign-extend and add
Datapath With Control
Processor Architecture 2 – Chang Liu 10
R-Type Instruction
31:26 25:21 20:16 15:11 10:5 5:0
op
rs
rt
Processor Architecture 2 – Chang Liu
rd sa funct
R format
11
Datapath With Control
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31:26 25:21 20:16 15:0
op
rs
rt
Load Instruction
Processor Architecture 2 – Chang Liu
immediate
I format
13
Datapath With Control
Processor Architecture 2 – Chang Liu 14
op
Branch-on-Equal Instruction
31:26 25:21 20:16 15:0
rs
rt
Processor Architecture 2 – Chang Liu
immediate
I format
15
2
address
Jump
Implementing Jumps
31:26 25:0
• Jump uses word address
• Update PC with concatenation of – Top 4 bits of old PC
– 26-bit jump address
– 00
• Need an extra control signal decoded from opcode
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Datapath With Control
Processor Architecture 2 – Chang Liu 17
31:26 25:0
Datapath With Jumps Added
op
jump target
Processor Architecture 2 – Chang Liu
J format
18
Main Control
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Mapping The Main Control Function to Gates
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Mapping The Main Control Function to Gates
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ALU Control
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Abstracted 32-Bit ALU • Final 32-Bit ALU
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ALU Control
• Assume 2-bit ALUOp derived from opcode
– Combinational logic derives ALU control
opcode
ALUOp
Operation
funct
ALU function
ALU control
lw
00
load word
XXXXXX
add
0010
sw
00
store word
XXXXXX
add
0010
beq
01
branch equal
XXXXXX
subtract
0110
R-type
10
add
100000
add
0010
subtract
100010
subtract
0110
AND
100100
AND
0000
OR
100101
OR
0001
set-on-less-than
101010
set-on-less-than
0111
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Implementing Combinational Control Units
Operation2 =1
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Mapping the ALU Control Function to Gates
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Mapping the ALU Control Function to Gates
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Mapping the ALU Control Function to Gates
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Memory and Registers
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ALU and Adders
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Multiplexers (Data Selectors)
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Sign Extension
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Control System
Processor Architecture 2 – Chang Liu 33
You Can Now Design and Build a Simple CPU
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Next Lecture
• A More Complex CPU • Pipelining
• Hazards
Processor Architecture 2 – Chang Liu 35