MOS Capacitance
• MOS structure
• MOS energy band diagram
• Effects of applied biases
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• *Voltage drops
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
MOS Capacitors ⚫ Whycapacitors
➢ Foundation for understanding MOS
transistors
⚫ Applications
➢ CCD camera
➢ Non-volatile memory
➢ Test structure during fabrication
➢ As a component
Metal Oxide(SiO2)
MOS Capacitor Structure
MOS capacitor (cross-sectional view)
Typical MOS capacitors and transistors in ICs today employ
heavily doped polycrystalline Si
(“poly-Si”) film as the gate- electrode material
n+-type, for “n-channel” transistors (NMOS)
p+-type, for “p-channel” transistors (PMOS)
SiO2 as the gate dielectric band gap = 9 eV
er,SiO2 = 3.9
Si as the semiconductor material
p-type, for “n-channel” transistors (NMOS)
n-type, for “p-channel” transistors
parallel-plate capacitor
⚫ Definition: C = ε A/t = εrεo A/t
where εr (SiO2) = 3.9, εo = 8.85 x 10-14 F/cm
MOS Capacitance Measurement
• Vb: dc biasing voltage and scanned slowly
DQ = DQ •V :smallacsignal m acc ac
•V=V+V g b ac
C= dQGATE = dQs = dQs dVg dVg dVac
• Capacitive current due
to V is measured ac
|Vb|>>|Vac|
MOS Capacitor
iac =CdVac dt
MOS Capacitance
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops
Reference reading: Chapter 6.0-6.4
Which one is the p-type Si?
Which one is the heavily doped Si?
Poly-Si gate
“metal” oxide semiconductor
Electron energy
n+ poly-Si
Coordinate system
metal oxide semiconductor
EC EgSi = E
EgSi = 1.1eV
1.1eV EFS EgSiO2 x
n+ poly-Si SiO2
Guidelines for Drawing MOS Band Diagrams
E0: vacuum energy level
cSiO2=0.95eV EC
Electron barrier
E0-EF : work function
E0-EC : electron affinity EV
cSi= 4.05eV
FS=cSi+ (EC-EFS) EC
Hole barrier
qVFB = FM- FS
Guidelines for Drawing MOS Band Diagrams 1) Fermi level EF is flat (constant with distance x) in the Si
➢ Since no current flows in the x direction, we can assume that equilibrium conditions prevail
2) Band bending is linear in the oxide
➢ No charge in the oxide => de /dx =r/eox= 0, so e is constant => dEC/dx is constant
e= – dV/dx EC=-qV
Guidelines for Drawing MOS Band Diagrams
3) The barrier height for conduction-band electron flow from the Si into SiO2 is 3.1 eV
➢ This is equal to the electron-affinity difference (cSi and cSiO2)
4) The barrier height for valence-band hole flow from the Si into SiO2 is 4.8 eV
5) The vertical distance between the Fermi level in the metal, EFM, and the Fermi level in the Si, EFS, is
equal to the
applied gate voltage:
qVG =EFS −EFM
MOS Equilibrium Energy-Band Diagram
metal oxide semiconductor
n+ poly-Si
EC EC=EFM EFS
Guideline 1: Fermi Level is flat.
MOS Equilibrium Energy-Band Diagram
Fermi Level is flat.
metal oxide semiconductor
Virtual “Cable”…
n+ poly-Si
Q2 EC EC=EFM EFS
After contact, there are two questions: Q1 & Q2.
Q1: Carrier and ion in silicon
Guideline 2:
metal oxide semiconductor
e=-dV/dx Ee=-qV
Q2: Carrier and ion in silicon
metal oxide semiconductor
EC EC=EFM Q2 EFS
n+ poly-Si
Q2: Carrier and ion in silicon
metal oxide semiconductor
EC EC=EFM Q2 EFS
EC Ei EF EV
n+ poly-Si SiO2
Flat-Band Voltage
metal oxide semiconductor
n+ poly-Si
Flat-Band Voltage
n+ poly-Si
⚫ The built-in potential can be “cancelled out” by applying a gate voltage that is equal in magnitude (but of the opposite polarity) as the built-in potential. This gate voltage is called the flatband voltage because the resulting potential profile is flat.
Flat-Band Condition Eo
VG = VFB ≈ -1V
qVG = EFS- EFM
= FM- FS VG = VFB
qVFB = FM- FS
MOS Capacitance
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops
Reference reading: Chapter 6.0-6.4
Ec(O) and electric field direction
-qV =Ec(O)
-qV =Ec(O)
Effects of applied biases
Vg increase from “-” to “+” :
1. Vg
Depletion: Majority carriers
4.1 VT>Vg>Vm
Weak Inversion: Minority carriers Strong Inversion: Minority carrier
What is VFB, Vm and VT?
1. Accumulation (p-type Si) : Vg
Depletion: Majority carriers
Physical process:
holes repelled from the interface fixed negative charge left behind
More “+” charges on the gate, holes are pushed further from the interface, to
expose more “-” space charges.
○: Hole : B-
3. Depletion:
Energy band diagram: Vg>VFB
The band is bent downward now. No mobile charges at the interface.
qVg = EFS – EFM
Vg>VFB EFM
-qV =Ec(O)
3. Depletion Capacitor
⚫ Capacitance tox
Higher potential
Vs (or fs)
Cox =eox tox
Cdep =eSi xd
When Vg increases, Xd increases and Cdep reduces. This in turn reduces C.
Solving Poisson’s equation, we have
1/2 2e V
x = Si S d qNa
Cdep =eSi xd
Cox =eox tox
3. Capacitance in Depletion
• As the gate voltage is varied, the width of the depletion
region varies.
Incremental charge is effectively added/subtracted at a
depth xd in the substrate. MOS
DQ C= Q xd
1 = 1 + 1 = 1 + xd C Cox Cdep Cox eSi
e Cox Cdep = Si
eSi=er’Sieo , er’Si=11.9 is the relative dielectric constant of silicon,.
3. Depletion:
Capacitance-voltage (C-V) characteristics
⚫ Example:p-Si C
Vb Inversion
Accumulation
Midband: further increase Vg
⚫ EFS = Ei = (Ec+Ev)/2 at interface
⚫ Silicon becomes “intrinsic” at surface
⚫ This is ‘Midband’: Vg=Vm
At the interface
qVg = EFS – EFM 4. Energy band diagram: Vg> Vg
Inversion:
Minority carriers
As Vg>Vm, EFS is at the up-half of the bandgap
At the interface
EFS Ec xd
Bulk Semiconductor Potential, fF qfF Ei −EF
⚫ p-typeSi:
fF =kTln(NA/ni)0 q
⚫ n-typeSi:
fF =−kTln(ND/ni)0 q
4. Inversion: large positive (Vg-VFB)
➢ Weak Inversion: 0
xdmax xdmax 51
MOS Capacitance
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops
Voltage dropped in the silicon
Surface Potential
qfS =Ei(bulk)−Ei(surface)
qfS = EC (bulk ) − EC (surface) qf =E (bulk)−E (surface)
qfS qV Ev G
Ec= EFM Ev
Vox is the voltage dropped across the oxide
Voltage Drops in the MOS System
Ec= EFM Ev
V =V +f ????????
V -V =SV +f G G oxFB ox
Voltage Drops in the MOS System
In general, where
qVFB =FMS =FM –FS
Vox is the voltage dropped across the oxide
(Vox = total amount of band bending in the oxide) fs is the voltage dropped in the silicon
(total amount of band bending in the silicon)
qfS =Ei(bulk)−Ei(surface)
For example: When VG = VFB, Vox = fs = 0 i.e. there is no band bending
V =V +V +f G FB ox s
Voltage Drops in the MOS System
V =V +V +f G FB ox s
V =V +V +2f T FB ox F
2qNDeSi Cox
V =V +2f − T FB F
2qNDeSi 2fF Cox
⚫ A MOS capacitor has:
Xox=40nm, Nd=1021m-3, fF=0.3V, eox=3.9, es=11.8
⚫ Determine:
(i) C(HF) in accumulation; (ii) C(HF) in strong inversion (iii) C(LF) in strong inversion
⚫ Solution:
(i) C(HF)= Cox=eoeox/Xox
=8.85E-123.9/4.0E-8 =8.63E-4 F/m2
(ii) In inversion VS=2fF=0.6V
xd=8.85E-7 m
Cs=eoes/xd =1.18E-4F/ m2 C(HF)=CoxCs/(Cox+Cs)=1.04E-4F/ m2
(iii) C(LF)=Cox=8.63E-4 F/m2
1/2 2e e V
qN d
⚫ An MOS capacitor is made on uniformly doped p type material. With -20V on the gate with respect to the substrate it has a capacitance of 20pF. With +20V on the gate it has a capacitance of 10pF. What is the thickness of the depletion layer if the capacitor has an area of 10-6m2.
⚫ Solution
⚫ With negative bias on the top electrode: C = Cox. (20pF)
⚫ With positive bias: 1/C = 1/Cox+1/Cs
⚫ since Cs=(1/C – 1/Cox)-1= (1/10 – 1/20 )-1 =20 pF. The thickness of the depletion layer xd is obtained from Cs=Aese0/ xd,
⚫ xd =10-6*12* 8.8*10-12/ 20*10-12 =5*10-6m
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