Digital System Design
Functional Design Register Transfer Level Design Logic Design
Circuit Design Physical Design
Top-down Digital System Design
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 1
Functional Design
Functional design is based on: Requirement specification
Target implementation influences the design flow CPU
ASIC (Application Specific Integrated Circuits) FPGA (Field Programmable Gate Arrays)
Requirements:
Operation, Performance, Interface, Cost, Size, Power dissipation…
Functional design may be verified through simulation
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 2
Register Transfer Level Design (RTL)
This step in the design flow transforms the high-level functional design into a description at the register level.
The Register Transfer Level Design describes the design at the following level of abstraction:
Registers Memory Arithmetic Units State Machines
RTL designs are validated through simulation
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 3
Logic Design
At this stage in the design flow the register level transfer design is compiled into logic design.
Again the design may be verified through simulation.
Please note:
Simulation may be used to guaranty that the design meets the specification.
The simulation in every step in the design flow allows for the interception of errors early in the design.
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 4
Circuit Design
At this stage in the design flow the logic design is compiled into circuit design.
The step is strongly influenced by the target implementation.
Again the design may be verified through simulation specifically through:
Timing simulation Circuit analysis.
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 5
Physical Design
In the final step in the design flow the circuit design determines the physical chip layout.
Physical properties may be verified: Chip area
Power dissipation Clock frequency
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 6
Digital System Design Hierarchy
Functional Design High
RTL Design Logic Design
Circuit Design
Low
Physical Design
Small number of R1 <- R1 +R2
Description
complex components
Level of abstraction
Gates Circuit
Transistor
Large number of simple components
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 7
Hardware Description Languages
Hardware Description Languages are used to: Describe digital systems
Model digital systems
Design digital systems
Hardware Description Languages: VHDL, Verilog and more
VHDL
VHSIC Hardware Description Language
VHSIC
Very High Speed Integrated Circuit Language
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 8
Target Implementation Design flow depends on target hardware
Algorithms
HDL
RTL
Logic Design
Circuit Design
Physical Design
ASIC
RTL
Logic Design
Circuit Design
Physical Design
FPGA
Assembly Code
Machine Code
CPU
Application Specific Integrated Circuits
CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 9
Design Views
Behavioural Algorithms
Register Transfers
Boolean Expressions
Transfer Functions
Transistors Gates
Register
Processor
Structural Cells
Modules
Chips
Boards Physical CSU22022, 1st HDL Lecture, Dr. M. Manzke, Page: 10