RT Description of the Datapath
RW: R[DA] If MD then
FS(R[AA], if MB then R[BA]
VCn Cn-1,
C Cn,
Z Rn-1,Rn-2,…,R0, N Rn-1,
else Constant in) else DATA in,
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 1
Symbolic Notation for Micro-ops
Because human beings working in binary code tend to be highly error-prone, we usually employ intuitive symbols to specify datapath micro-ops.
Typical symbol/code assignments are:
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 2
DA, AA, BA
MB FS Function Code Function Register 0 G=A Constant 1 G=A+1
Function Code
Code
R0 00000
00000 00001
R1 00001
R2 00010
G=A+B MD G=A+B+1
00010
00011
00100
00101
00110
00111
01000
01010
01100
01110
10000
10100
11000
R3 00011
R4 00100
Function Code G=A+B Function 0 G=A+B+1 Data In 1 G=A–1
R5 00101
R6 00110
R7 00111
G=A RW G=AB Function Code G=AB
continue
R31 11111
No Write 0 G=AB Write 1 G=A G=B
Symbol-binary Map of Control Word Fields
G=srB G=slB
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Symbol Conversion
With the symbolic notation it is easy to accurately specify control words which may then be automatically converted to binary.
For example: R1R2 + R3 +1 8 Register Example
Field: DA AA BA MB FS MD RW
Symbol: R1 R2 R3 Register F=A+B+1 Function Write
Binary: 001 010 011 0 00101 0 1
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Microoperations Example
DIY – Convert these to binary and check your results against the table on the next slide.
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Binary Control Words from Example 8 Register Example
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Examine the figure:
Register transfer on Clock .
R0 – R7 are initialised to Rii.
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Status Bits
Status bits shows the input for the Zero, Negative, Carry-out and Overflow bits respectively.
Hence the change following a control word change.
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T
Q
Register with delay tr
Datapath Timing
The total, worst case propagation delay determines the maximum rate at which we may clock a system.
tp
Combinational logic with delay tp
tr R D
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T
Q
Timing
For successful operations we must have:
tp
T tp + tr Tmin = tp + tr fmax = 1 / Tmin
tr R D
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tr = 1ns
tp = 3+1+4+1+2ns
= 11ns Tmin = 12ns
fmax = 1 / Tmin
= 83.3MHz
Conventional and Pipelined Datapath Timing
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TP
Tp/3
fmax = 1 / Tmax =200MHz
Three-Stage Pipeline
tr
D
P2
tr
D
P1
Tp/3 Q
To speed things up we can introduce register into the combinational logic.
Tp/3 Q
TP tp/3+tr Tmax = 1+4ns
Q
tr R D
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Pipelined Datapath
When a datapath is pipelined it divides naturally into stages seen on the next slide.
OF = Operand Fetch EX = Execute
WB = Write Back
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Pipelined Datapath Schematic
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Pipe Execution Pattern
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