Arithmetic Circuit
The arithmetic circuit may implemented with the following components:
Parallel Adder
Build from a cascade of full-adder circuits
The data input to the parallel adder is manipulated in order to achieve a number of arithmetic operations
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N-bit Arithmetic/Logic Unit(ALU)
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0 0
0 1
1 0
1 1
all 0’s B
B
all 1’s
G=A G=A+1 G=A+B G=A+B+1 G=A+B G=A+B+1 G=A-1 G=A
G = A + Y + Cin
The arithmetic micro-ops can be implemented using the carry-in Cin and two select inputs S1 & S0, which condition the B input to deliver Y to the full-adder computing: G = A + Y + Cin.
Select
S1 S0
Input
Y
Cin=0 Cin=1
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Arithmetic Circuit
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Y(S,B)
The logic function Y(S,B) is derived as:
Yi=S0Bi+S1 Bi
Thus a 2:1 MUX controlled by Bi can efficiently generates Yi
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One Bit Slice
One bit slice of the Arithmetic unit on the next slide.
Bi S MUXi Ai
Yi Ai
Ci FAi
Gi
S1 S2 01
Ci+1
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4-Bit Arithmetic Circuit
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Logic Circuit
The logic function are similarly selected by input S1 and S0 :
Select
S1 S0
Output
0 0
0 1
1 0
1 1
G=AB AND G=AB OR G=AB XOR G=A NOT
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Logic Circuit
Implemented with a 4:1 MUX
One bit slice of the logic unit.
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ALU (Arithmetic/Logic)
We next use an additional 2:1 MUX controlled by S2 to select either the arithmetic output bit or the logic output bit as shown on the next slide.
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One bit slice ALU
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N-bit ALU
To construct an n-bit ALU we concatenate n-bit slices together:
S0 S1CinS2
B0 G A0 0
B1 G A1 1
Bn-1 An-1
Gn-1 Cout
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Physical Implementation
Physical schematic of an n-bit ALU assembled from a bit slices as shown on the previous slide.
1. Note the control signals, because they apply to the whole word, tend to cross the datapath.
2. This geometry results in very efficient VLSI chip implementation.
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0 0 0 0
0 0 0 1
G=A TRANSFER G=A+1 INCREMENT
0 0 0 0 0 1 0 1 0 1
0 1
1 0
1 0 1 1 1 1
1 0 1 1 0 0 0 1 1 0 1 1 0 X 1 X 0 X 1 X
G=A+B ADD G=A+B+1 ADD WITH C G=A+B A plus 1’s C.B G=A+B+1 SUBTRACT G=A-1 DECREMENT G=A TRANSFER G=AB AND G=AB OR
G=AB XOR
G=A NOT
Adder
This adder this gives us a fast combinational ALU with the following functionality:
Select
S2 S1 S0 Cin
Output
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4-Bit SR/SL Shifter Unit
For speed of execution the shifter unit is always implemented as a combinational circuit based on a MUX:
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