Basic Computer Architecture
Computers consist of: Datapath
Control unit
It is designed to implement a particular instruction set.
The individual instructions are the engineering equivalent of the mathematician’s
z=f(x,y)
f z x,y
OPCODE DESTINATION OPERANDS
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Opcode – Destination -Operands
OPCODE
Selects the function
DESTINATION
Is nearly always a datapath register
OPERANDS
Usually come from datapath register
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Instruction Format Examples
Register
31 1514109540
Immediate
31 1514109540
Jump and Branch
31 1514109540
Opcode
Destination Register (DR)
Source Register (SA)
Source Register (SB)
Opcode
Destination Register (DR)
Source Register (SA)
Operand (OP)
Opcode
Address (AD) (Left)
Source Register (SA)
Address (AD) (Right)
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Instruction Formats
Where DR, SA SB point to processor registers in the datapath
But Operand is itself an immediate operand
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Data and Instructions in Memory
Example for a 16 Bit processor, with 7, 3, 3, 3 bits
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User View of Storage
Register File 32 x 32
Instruction Memory
232 x16
Program Counter (PC)
Data Memory
232 x16
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Memory Module [entity]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity memory is — use unsigned for memory address
Port ( address : in unsigned std_logic_vector(31 downto 0); write_data : in std_logic_vector(31 downto 0); MemWrite, MemRead : in std_logic;
read_data : out std_logic_vector(31 downto 0));
end memory;
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Memory Module [architecture]
architecture Behavioral of memory is
— we will use the least significant 9 bit of the address – array(0 to 512) type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
— define type, for memory arrays
begin
mem_process: process (address, write_data)
— initialize data memory, X denotes hexadecimal number
variable data_mem : mem_array := (
X”00000000″, X”00000000″, X”00000000″,X”00000000″, X”00000000″, X”00000000″, X”00000000″,X”00000000″);
variable addr:integer
begin — the following type conversion function is in std_logic_arith addr:=conv_integer(address(2 downto 0));
if MemWrite =’1′ then
data_mem(addr):= write_data;
elsif MemRead=’1′ then
read_data <= data_mem(addr) after 10 ns;
end if;
end process;
end Behavioral;
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A Single-cycle Hardwired Control Unit
We briefly consider a system with the simplest possible control unit.
The control unit:
Maps each OPCODE to a single datapath operation.
Instructions are fetched from an instruction memory
This is what all present systems with separate instruction and data code do.
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Single-Cycle Computer
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Branch
Instruction Bit13=1 Jump occurs
Instruction Bit13=0
Conditional Branch occurs
Bit11, Bit10 and Bit9 Select the status bit
BC Status Bit
000 C
001 N
010 V
011 Z
100 C
101 N
110 V
111 Z
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Jump and Branch
PL=1
Jump or Branch, loading the PC
PL=0
PC is incremented
PL=1 JB=0 Jump
PL=1 JB=1 Conditional branch
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Truth Table BIT15 – BIT13
The following operations classification helps with the implementation of the instruction decoder
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Instruction Decoder
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Single-Cycle Computer Instruction Example
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Single-cycle Problem
A single-cycle control unit cannot implement:
more complex addressing modes
Composite functions E.g. Multiplication
A single-cycle control unit has long worst case delay path.
Slow clock.
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Worst Case Delay
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Multiple-Cycle Microprogrammed Computer
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
76543210 MUX S
PC
Extend
D
(32+1) x 32 Register file
AB
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
IR Opcode |DR|SA|SB
Zero Fill
01 MUX C
10 MUX B
01 MUX M
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
17
4
MW
CAR
32
32
1
17
C1 4N1
V - C - N - Z
AB
Function Unit
F
Data In Address
(2^32) x 32 Memory M
Data Out
Control Memory (2^17) x 42
Sequence Control Datapath Control
Z
FS
1 1 5
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF ASCLILDABBSDWMWVCNZL
FL
32
Data
Instructions
01 MUX D
MD
1 Bus D
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Microinstruction Format
Control Memory
(2^17) x 42
Sequence Control Datapath Control
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF ASCLILDABBSDWMWVCNZL
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Control Word Information for Datapath
Example, our project is different!
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