Multiple-Cycle Design
The Multiple-Cycle Implementation demonstrates the use of a single memory for:
Data Instruction
This design is also used to show the implementation of more complex instructions
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 1
Memory M Address
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
The following address sources are used to fetch: Instructions -> PC Program Counter Register (32bit) Data -> Bus A (32bit)
MUX M selects between the two address sources through the MM control signal
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 2
PC – Bus A – MM
Extend
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
D
(32+1) x 32 Register file
AB
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
IR Opcode |DR|SA|SB
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
76543210 MUX S
Zero Fill
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
CAR
32
32
1
17
C1 4N1
1 1 5
AB
Function Unit
F
01 MUX M
V – C – N – Z
Data In Address
(2^32) x 32 Memory M
Data Out
Control Memory (2^17) x 42
Sequence Control Datapath Control
Z
FS
FL ASCLILDABBSDWMWVCNZL BusD
32
Data
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF
MD
1
01 MUX D
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 3
Temp Register
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
Instructions are executed over multiple clock cycles
This requires an additional register R32 for temporary storage
This register should be selected through an additional bit control signals:
TD, TA, TB
The overwrite:
SA, SB, DR
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 4
TD||DR –TA||SA – TB||SB
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
1+5 TB||SB
Bus A Data Address
76543210 MUX S
PC
Extend
D
(32+1) x 32 Register file
AB
32
RW TD||DR 1+5
TA||SA
1
IR Opcode |DR|SA|SB
IL
3 MS 17
17
1
Zero Fill
32 555 1+5
1 MB MM
Bus B
32
01 MUX C
10 MUX B
DR SA SB
RV || RC || RN || RZ
4
Reset
V
1
32 1 32
32
MW
1
17
C1 4N1
1 1 5
AB
Function Unit
F
01 MUX M
Control Memory (2^17) x 42
Sequence Control Datapath Control
CAR
V – C – N – Z
Z
FS
Data In Address
(2^32) x 32 Memory M
Data Out
FL ASCLILDABBSDWMWVCNZL BusD
32
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
Data
MD 1
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 5
01 MUX D
NMMIPP TTTMFMRMMRRRRF
IR Instruction Register
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
Instructions must be held in a register during the execution of multiple micro-ops
The IR is only loaded if an instruction is fetched from memory M
The IR has a load enable control signal IL This signal is part of the control word
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 6
PC Program Counter Register
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
The PC only increments if an instruction is fetched from memory M
The control word has two bits that determine the PC modifications:
PI – increment enable signal
PC PC + 1
PL – PC load signal
PC PC + se AD
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 7
IR – IL; PC – PI – PL
Extend
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
D
(32+1) x 32 Register file
AB
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
IL
1
MS
1
32
V
1+5 TB||SB Data Address
IR Opcode |DR|SA|SB
76543210 MUX S
3
17
Zero Fill
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
1
17
C1 4N1
1 1 5
32
32
AB
Function Unit
F
01 MUX M
CAR
V – C – N – Z
Data In Address
(2^32) x 32 Memory M
Data Out
Control Memory (2^17) x 42
Sequence Control Datapath Control
Z
FS
FL ASCLILDABBSDWMWVCNZL BusD
32
Data
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF
MD
1
01 MUX D
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 8
Next Address Logic
44333333333322222 10987654321098765
Next Address
222 432
MS
2 1 M C
2 0 I L
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
The CAR Control Address Register selects the control word in the 256 x 42 control memory
The next logic (MUX S) determines whether CAR is incremented on loaded.
Controlled with MS
The source (Opcode or NA) of the loaded address is determined by MUX C
Selected by MC
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 9
Next Address Field
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
The sources for the multiplexer can be: Contents of the 17 bit NA Next Address field 17 bit from the opcode field in the IR
An opcode loaded into the CAR points to: Microprogram in Control Memory
This program implements the instruction through the execution of a sequence of micro-operations
MUX S determines whether the CAR is: Incremented
Loaded
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 10
Sequencer Control Fields
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 11
NA – MS – MC
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
IR Opcode |DR|SA|SB
Extend
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
D
(32+1) x 32 Register file
AB
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
76543210 MUX S
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
Control Memory (2^17) x 42
Sequence Control Datapath Control
Zero Fill
32
32
1
17
C1 4N1
1 1 5
AB
Function Unit
F
01 MUX M
CAR
V – C – N – Z
Data In Address
(2^32) x 32 Memory M
Data Out
Z
FS
FL ASCLILDABBSDWMWVCNZL BusD
32
Data
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF
MD
1
01 MUX D
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 12
C116
Microprogram ASM
R[DR]←R[SA]+zf IR[4:0]
C016
0016
0116
0216
0316
0416
0516
Implementation on page14
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 13
Microprogram in Control Memory
?=02 or?=12
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0|
— | Next Address | MS | M| I| P| — | Next Address | MS | C| L| I|
— ADI R[DR]←R[SA]+zf
“000000000??????????? ? ? ? — LD R[DR]←M[R[SA]]
“000000000??????????? ? ? ? — ST M[R[SA]]←R[SB]
“000000000??????????? ? ? ? — INC R[DR]←R[SA]+1 “000000000??????????? ? ? ?
P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
IR[4:0]
?
?
?
?
? ? ? ? ? ? ? ? ? ?
? ???????????????”,–00 ? ???????????????”,–01 ? ???????????????”,–02 ? ???????????????”,–03 ? ???????????????”,–04 ? ???????????????”,–05
? ???????????????”,–C0 ? ???????????????”,–C1
);
variable control_out : std_logic_vector(41 downto 0);
— NOT R[DR]←NOT[R[SA]]
“000000000??????????? ? ? ? ? — ADD R[DR]←R[SA]+R[SB]
“000000000??????????? ? ? ? ? ? ?
— IF IR←M[PC], PC←PC+1
“000000000??????????? ? ? ? ? ? ? — EX0 CAR←IR[31:15]
“000000000??????????? ? ? ? ? ? ?
• • •
• • •
variable addr : integer;
CSU22022, 16th Lecture, Dr. M. Manzke, Page: 14