CS计算机代考程序代写 flex algorithm Overflow

Overflow
When we use fixed size Register for arithmetic operands there is the hazard at each micro-ops of overflow.
If Register R stores an n-bit 2’s compliment number, then:
-2n-1  R  2n-1-1
Note the asymmetry, so even negation can cause overflow,
e.g.
R  -2n-1 then R  -R  OVERFLOW CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 1

Carry and Overflow
We can detect overflow for all the previous operations simply by recording the status bits C = Carry and V = Overflow (see section 3.10 I Mano and Kime).
K1:CCn,VCn Cn-1
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 2

Adder-Subtractor
This then is the basis for the adder-subtractor on the next page which uses control input X to select addition and X for subtraction.
X.K1: R1  R1 + R2 X.K1: R1  R1 + R2 +1
K1:CCn,VCn Cn-1
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 3

Add & Subtract Micro operation
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 4

Symbolic micro-op
Description
Logic Micro-operations
The aim here is to provide an effective set of bit-wise functions. A typical basic set follows:
R0R1 R0R1  R2 R0R1  R2 R0  R1  R2
Logical bitwise NOT (1’s compliment) Logical bitwise AND (clears bits) Logical bitwise OR (sets bits)
Logical bitwise XOR (complements bits)
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 5

 And 
George Bode Prof. Of mathematics in UCC introduced the notation ‘’ and ‘’ in 1854, and they are used in Register Transfer (RT) notation if it is necessary to distinguish addition from logical OR. For example:
K1 + K2 : R1R2+R3, R4R5  R6 Logical OR Logical OR
addition The OR micro-ops will always use .
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 6

The minimal set is:
Shift Micro-operations
These provide lateral bitwise shift which are essential for many basic arithmetic algorithms e.g. multiplication division , square root…
R sr R  RiRi+1 i=0, n-2, Rn-10 R sl R  RiRi-1 i=1, n-1, R00
CSU22022, 3rd Lecture, Dr. M. Manzke, Page: 7

Logical Shifts
These are logical shifts and from them you can develop variants which handle the end bits differently, e.g. arithmetic shift, rotates…
Please see table 9-5 in Mano and Kime.
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Transfer Micro-operations
Providing choice of path
Two approaches are used: Multiplexer-based transfer for speed
Bus-based transfers for flexibility and economy
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Transfer with Multiplexer
The if-then else control structure, when applied to identity micro-ops, results in the destination register requiring selective access to two different source registers.
If (K1=1) then R0R1
else if (K2=1) then R0R2
K1: R0R1,K1K2:R0R2
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Two Sources – One Destination
To route two sources to one destination we can use a 2:1 MUX with control input S, data input D0  D1, and R0 must have a load control LOADR0.
From the RT description we deduce the following functions for these control inputs.
LOADR0 = K1+ K1K2 = K1+ K2 S = K1  D1 = R1  D0 = R2
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Multiplexer
From this we derive the circuit schematic, assuming 4- bit Registers.
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Multiplexer Detail
Note changes in K1 only affect the MUX – R0 path, so transients are short, allowing fast operation.
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