For example:
Register Transfer
Describing large-scale processor activity.
To discuss digital systems of this scale and level of complexity we need a number of descriptive tools.
a) Circuit schematics highlight the circuit components and their connectivity.
CSU22022, 2nd Lecture, Dr. Manzke, Page: 1
Transfer from R1 to R2 when K1=1 Circuit Schematic
K1
R1 n R2
Clock
Datapath
CSU22022, 2nd Lecture, Dr. Manzke, Page: 2
R2
R2 = R1
Timing Diagram
b) Timing diagrams highlight the detailed time sequence of transfer between registers.
K1 Clock
R2 previous value
R2 <- R1
The transfer R2 <-r1 occurs at the end of K1
CSU22022, 2nd Lecture, Dr. Manzke, Page: 3
i.e. K1 K1.CLOCK
State Diagram
c) State diagrams highlight the modes of operation and their control
IDLE
K1
R2<-R1
K1
LOAD
When the system is synchronous we normally omit the clock specification.
CSU22022, 2nd Lecture, Dr. Manzke, Page: 4
Register Transfer Specification
Source Register Destination Register Operation to be applied
Condition or control function under which the transfer will occur.
We assume synchronous operation and omit the clock
Operation
K1 : R2 <- R1
Control Function Source Register Destination Register
CSU22022, 2nd Lecture, Dr. Manzke, Page: 5
Building Register-Transfer Statements
Symbol(s)
Description
Examples
Letters and Numerals
Denote Registers
AR, DR, R2, IR
Parentheses Arrow
Comma
Square brackets
Denote sections of Registers
R2(9), AR(2),R1(7:0)
Denotes data transfer
R1<-R2 IR<-DR
Separates simultaneous transfers
R1<-R2, R3<-AR
Denote memory addressing
DR<-M[AR]
/* a read
M[AR]<-DR
/* a write
CSU22022, 2nd Lecture, Dr. Manzke, Page: 6
Operation
RTL VHDL
Combinational Assignment Register Transfer Addition Subtraction Bitwise AND Bitwise OR Bitwise XOR Bitwise NOR
Shift left (logical) Shift right (logical) Vector/Register Concatenation
= <=(concurrent)
VHDL and RTL
<=(concurrent) + +
- -
^ and
or
xor
̄ not
sl sll
sr srl
A(3:0) A(3 downto 0) || &
CSU22022, 2nd Lecture, Dr. Manzke, Page: 7
Micro-Operation
A micro-operation is an operation which can be accomplished within a small number of gate propagation delays upon data stored in adjacent registers and memory.
Those commonly encountered in digital systems divide naturally into four groups
Transfer or identity micro-ops copy data, e.g. R1<-R2, DR<-M[AR]
Arithmetic micro-ops provide the elements of arithmetic, e.g. R0<- R1+R2
Logic micro-0ps provide per bit opearation, e.g. R1<-R2 or R2 Shift micro-ops provide bit rotations, e.g. R1<-sr R2, R0<- rol R1
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Arithmetic Micro-ops
These are operations which can be accomplished with a full-adder, which, with carry lookahead logic, can be made to deliver a substantial result, e.g. 64-bit in just a few gate delays.
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Carry Lookahead Adder
CSU22022, 2nd Lecture, Dr. Manzke, Page: 10
CLA
Let R0, R1,R3 be n-bit Register and consider what can be done with an n-bit CLA (carry lookahead adder)
From Register Ouput nn
AB
Ci S
To Register Input
CSU22022, 2nd Lecture, Dr. Manzke, Page: 11
Conditioned use of CLA By conditioning what arrives at A,B,Ci we can achieve:
Symbolic CLA Inputs micro-op A B C
Function S
R0<-R1+R2 R0<-R1-R2 R0<-R1+1 R0<-R1-1 R0<-R2 R0<-R2
R1 + R2 + 0 R1+R2+1 R1+0...0+1 R1+1...1+0 0...0 + R2 + 0 0...0 + R2 + 1
Addition Subtraction Increment Decrement
1’s Complement 2’s Complement
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Add &Sub Implementation
The first two of these operations may be accomplished by the addition of an XOR gate to the B-input of each full-adder, as show on the next page.
CSU22022, 2nd Lecture, Dr. Manzke, Page: 13
Adder-Subtractor Circuit
CSU22022, 2nd Lecture, Part II, Dr. Manzke, Page: 14