Tutorial 2
Tutorial 2
LC-3 instruction
Exercise (Hexadecimal addition)
0x07A6 + 0xA2BA 0xA06F + 0x0AA0
07A6 A06F
+ A2BA + 0AA0
Solution
07A6 A06F
+ A2BA + 0AA0
AA60 AB0F
LC-3 instruction process
Fetch instruction
Decode instruction
Evaluate address
Fetch operands
Execute operation
Store result
Terms
IR: Instruction Register
PC: Program Counter
DR: Designation register
SR: Source register
Opcodes – LC-3
4-bit opcode
15 different operations
3 types of instruction
Operate instructions: ADD, AND, NOT
Data movement instructions: LD, LDI, ST, STI, STR, LDR, LEA
Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP
4-bit opcode
15 different operations
3 types of instruction
Operate instructions: ADD, AND, NOT
Data movement instructions: LD, LDI, ST, STI, STR, LDR, LEA
Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP
Operate instructions – NOT
Assembler format
NOT DR, SR
Machine code format
Only has register mode for NOT operation
Opcode DR SR Redundancy
[15:12] [11:9] [8:6] [5:0]
1001 XXX XXX 111111
Operate instructions – ADD
Assembler format
Register mode: ADD DR, SR1, SR2
Immediate mode: ADD DR, SR1, Imm5
Machine code format
Opcode DR SR1 Mode Redundancy SR2
[15:12] [11:9] [8:6] [5] [4:3] [2:0]
0001 XXX XXX 0 00 XXX
Opcode DR SR1 Mode Immediate value
[15:12] [11:9] [8:6] [5] [4:0]
0001 XXX XXX 1 XXXXX
Register mode
Immediate mode
Operate instructions – AND
Assembler format
Register mode: AND DR, SR1, SR2
Immediate mode: AND DR, SR1, Imm5
Machine code format
Opcode DR SR1 Mode Redundancy SR2
[15:12] [11:9] [8:6] [5] [4:3] [2:0]
0101 XXX XXX 0 00 XXX
Opcode DR SR1 Mode Immediate value
[15:12] [11:9] [8:6] [5] [4:0]
0101 XXX XXX 1 XXXXX
Register mode
Immediate mode
Exercise 1
What should be the value of R1 if the following program is executed (based on the initial register status)?
Program:
AND R3, R3, #0
NOT R4, R2
AND R5, R4, R4
ADD R3, R3, R2
ADD R1, R1, #-8
Initial Registers Status:
R0: x0028
R1: x0006
R2: x0003
R3: x0012
Solution 1
AND R3, R3, #0
R3 <= (R3) and (#0)
AND instruction, immediate mode
R3 = x0012 = 0000 0000 0001 0010
#0 = x0000 = 0000 0000 0000 0000
(x0012) AND (x0000) = x0000
Store the result back to R3
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 x0000
R5 x0000
R0 x0028
R1 x0006
R2 x0003
R3 x0012
R4 x0000
R5 x0000
Solution 1
NOT R4, R2
R4 <= not(R2)
NOT instruction, register mode
R2 = x0003 = 0000 0000 0000 0011
NOT (x0003) = 1111 1111 1111 1100 = xFFFC
Store the result back to R4
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 xFFFC
R5 x0000
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 x0000
R5 x0000
Solution 1
AND R5, R4, R4
R5 <= (R4) and (R4)
AND instruction, register mode
R4 = xFFFC = 1111 1111 1111 1100
(xFFFC) AND (xFFFC) = xFFFC = 1111 1111 1111 1100
Store the result back to R5
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 xFFFC
R5 xFFFC
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 xFFFC
R5 x0000
Solution 1
ADD R3, R3, R2
R3 <= R3 + R2
ADD instruction, register mode
R3 = x0000 = 0000 0000 0000 0000
R2 = x0003 = 0000 0000 0000 0011
(x0000) + (x0003) = x0003
Store the result back to R3
R0 x0028
R1 x0006
R2 x0003
R3 x0003
R4 xFFFC
R5 xFFFC
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 xFFFC
R5 xFFFC
Solution 1
ADD R1, R1, #-8
R1 <= R1 + (-8)
ADD instruction, immediate mode
R1 = x0006 = 0000 0000 0000 0110
-8 = xFFF8 = 1111 1111 1111 1000
(x0006) + (xFFF8) = xFFFE
Store the result back to R1
R0 x0028
R1 xFFFE
R2 x0003
R3 x0003
R4 xFFFC
R5 xFFFC
R0 x0028
R1 x0006
R2 x0003
R3 x0003
R4 xFFFC
R5 xFFFC
2’s complement number
Final answer: R1 = xFFFE
Data movement instructions – LD
Assembler format
PC-relative mode: LD DR, PCoffset9
Machine code format
Load data from memory to register
DR = mem[PC + SEXT(PCoffset9)]
Opcode DR PCoffset9
[15:12] [11:9] [8:0]
0010 XXX XXXXXXXXX
SEXT = Sign extension
PC = Program counter (after fetch)
Data movement instructions – ST
Assembler format
PC-relative mode: ST SR, PCoffset9
Machine code format
Store data from register to memory
mem[PC + SEXT(PCoffset9)] = SR
Opcode SR PCoffset9
[15:12] [11:9] [8:0]
0011 XXX XXXXXXXXX
Data movement instructions – LDI
Assembler format
Indirect Addressing Mode: LDI DR, PCoffset9
Machine code format
Load data from memory to register
DR = mem[mem[PC + SEXT(PCoffset9)]]
The effective address of the operand is the contents of memory location, location whose address appears in the instruction.
Opcode DR PCoffset9
[15:12] [11:9] [8:0]
1010 XXX XXXXXXXXX
Data movement instructions – STI
Assembler format
Indirect Addressing Mode: STI SR, PCoffset9
Machine code format
Store data from register to memory
mem[mem[PC + SEXT(PCoffset9)]] = SR
The effective address of the operand is the contents of memory location, location whose address appears in the instruction.
Opcode SR PCoffset9
[15:12] [11:9] [8:0]
1011 XXX XXXXXXXXX
Exercise 2
What should be the value at register R2 if the following program is executed (based on the initial memory status)?
Program:
.ORIG x2000 ; The first instruction is at x2000
LD R1, #2 ; This is the first instruction
LD R2, #0
ST R1, #15
ST R2, #15
STI R1, #1
LDI R2,#0
Initial Memory Status:
x2000: x2202
x2001: x2400
x2002: x320F
x2003: x340F
x2004: xA20D
x2005: xA40D
X2006: x2005
Starting from x2007, all of them are x0000
Solution 2
LD R1, #2
PC-relative mode
PC (before fetch): x2000
PC (after fetch): x2001
DR = mem[PC + SEXT(PCoffset9)]
PC (after fetch) + SEXT(#2) = x2001 + x0002 = x2003
R1 = mem[x2003] = x340F
Register Content
R1 x340F
R2 ????
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
Register Content
R1 ????
R2 ????
Solution 2
LD R2, #0
PC-relative mode
PC (before fetch): x2001
PC (after fetch): x2002
DR = mem[PC + SEXT(PCoffset9)]
PC (after fetch) + SEXT(#0) = x2002 + x0000 = x2002
R2 = mem[x2002] = x320F
Register Content
R1 x340F
R2 x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
Register Content
R1 x340F
R2 ????
Solution 2
ST R1, #15
PC-relative mode
PC (before fetch): x2002
PC (after fetch): x2003
mem[PC + SEXT(PCoffset9)] = SR
SR = R1 = x340F
PC (after fetch) + SEXT(#15) = x2003 + x000F = x2012
Mem[x2012] = x340F
Register Content
R1 x340F
R2 x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
… …
x2012 x340F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
… …
x2012 x0000
Solution 2
ST R2, #15
PC-relative mode
PC (before fetch): x2003
PC (after fetch): x2004
mem[PC + SEXT(PCoffset9)] = SR
SR = R2 = x320F
PC (after fetch) + SEXT(#15) = x2004 + x000F = x2013
Mem[x2013] = x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
… …
x2012 x340F
x2013 x320F
Register Content
R1 x340F
R2 x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
… …
x2012 x340F
x2013 x0000
Solution 2
STI R1, #1
PC-relative mode
PC (before fetch): x2004
PC (after fetch): x2005
mem[mem[PC + SEXT(PCoffset9)]] = SR
SR = R1 = x340F
PC (after fetch) + SEXT(#1) = x2005 + x0001 = x2006
Mem[x2006] = x2005
Mem[x2005] = x340F
Register Content
R1 x340F
R2 x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 x340F
x2006 x2005
… …
x2012 x340F
x2013 x320F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 xA40D
x2006 x2005
… …
x2012 x340F
x2013 x320F
Solution 2
LDI R2, #0
PC-relative mode
PC (before fetch): x2005
PC (after fetch): x2006
DR = mem[mem[PC + SEXT(PCoffset9)]]
PC (after fetch) + SEXT(#0) = x2006 + x0000 = x2006
Mem[x2006] = x2005
Mem[x2005] = X340F
DR = R2 = X340F
Register Content
R1 x340F
R2 x340F
Memory address Content
x2000 x2202
x2001 x2400
x2002 x320F
x2003 x340F
x2004 xA20D
x2005 x340F
x2006 x2005
… …
x2012 x340F
x2013 x320F
Register Content
R1 x340F
R2 x320F
Exercise 3
The LC-3 does not have an opcode for the logical function OR.
However, we can write a sequence of instructions to implement OR.
The four-instruction sequence below performs the OR of the contents of register 1 and register 2 and puts the result in register 3.
Fill in the two missing instructions so that the four-instruction sequence will do the job:
(1): 1001 100 001 111111
(2):
(3): 0101 110 100 000 101
(4):
Hint : Use DeMorgan’s law
Solution 3
The LC-3 does not have an opcode for the logical function OR.
However, we can write a sequence of instructions to implement OR.
The four-instruction sequence below performs the OR of the contents of register 1 and register 2 and puts the result in register 3.
Fill in the two missing instructions so that the four-instruction sequence will do the job:
(1): 1001 100 001 111111 (NOT R4 R1)
(2): 1001 101 010 111111 (NOT R5 R2)
(3): 0101 110 100 000 101 (AND R6 R4 R5)
(4): 1001 011 110 111111 (NOT R3 R6)
Hint : Use DeMorgan’s law
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