Tutorial 3
Tutorial 3
LC-3 instruction (2) & Simulator GUide
LC3 simulator
Link to Simulator:
https://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/lc3guide.html
Follow the instructions on the page to set up the executable file
Important Java Version Commands
LOAD X
– Loads the object file X
As X
– Assemble the assembly file X
RESET
– Resets the simulator (You’ll need to reload the OS)
CLEAR
– Clears the command console
How to run a program?
Stepwise instructions on running an assembly program:
Use any editor (eg notepad++) to write the program
Save with some name with the file extension “.asm” i.e. “filename.asm”
Download the java version of LC3 from slide 2, ensure it is saved in the same file as your code from step 2
Execute the LC3.jar file
ON FIRST RUN
Step 3 on link, download the LC3-OS
Type “as lc3os.asm” into the command line
This will assemble the OS file
How to run a program?
Stepwise instructions on running an assembly program:
Assemble your code using “as filename.asm”; this will generate a file called “filename.obj” in the same folder
Load your object file using “load filename.obj”; additionally, you can load any data files you may do at this stage as well
Load the lc3os.obj file using “load lc3os.obj”
Loading the OS
Loading the OS
Use Next to run through each instruction on each line one by one
Use Continue to run all instructions all at once
Output values are displayed here
LC-3 instruction
Operate instructions: ADD, AND, NOT
Data movement instructions: LD, LDI, ST, STI, STR, LDR, LEA
Control instructions: BR, JMP, RTI, TRAP, JSR/JSRR
Data movement instructions – LDR
Assembler format
Base + Offset Mode: LDR DR, Base, offset6
Machine code format
Load data from memory to register
DR = mem[base register + SEXT(offset6)]
Opcode DR Base offset6
[15:12] [11:9] [8:6] [5:0]
0110 XXX XXX XXXXX
Content of base register
Data movement instructions – STR
Assembler format
Base + Offset Mode: STR SR, Base, offset6
Machine code format
Store data from register to memory
mem[base register + SEXT(offset6)] = SR
Opcode SR Base offset6
[15:12] [11:9] [8:6] [5:0]
0111 XXX XXX XXXXX
Data movement instructions – LEA
Assembler format
LEA DR, PCoffset9
Machine code format
Load (PC + PCoffset) to register
DR = PC + SEXT(PCoffset9)
Opcode DR PCoffset9
[15:12] [11:9] [8:0]
1110 XXX XXXXXXXXX
Exercise 1
What should be the value of R1 if the following program is executed (based on the initial register status)?
Program:
.ORIG x3000 ; The first instruction is at x3000
AND R0, R0, #0
ADD R2, R0, #2
ADD R3, R0, #3
LEA R1, #9
STR R3, R1, #3
STR R2, R1, #4
LDR R2, R1, #3
LDR R3, R1, #4
Initial Registers Status:
R0: x0000
R1: x0000
R2: x0000
R3: x0000
R4: x0000
Solution 1
AND R0, R0, #0
AND instruction, immediate mode
R0 <= (R0) AND (x0000)
Set R0 to x0000
Store the result back to R0
R0 x0028
R1 x0006
R2 x0003
R3 x0000
R4 x0000
R5 x0000
R0 x0000
R1 x0000
R2 x0000
R3 x0000
R4 x0000
R5 x0000
Solution 1
ADD R2, R0, #2
ADD instruction, immediate mode
R2 <= R0 + x0002
R0 = x0000 = 0000 0000 0000 0000
#2 = x0002 = 0000 0000 0000 0010
(R0) ADD (#2) = x0002
Store the result back to R2
R0 x0000
R1 x0000
R2 x0002
R3 x0000
R4 x0000
R5 x0000
R0 x0000
R1 x0000
R2 x0000
R3 x0000
R4 x0000
R5 x0000
Solution 1
ADD R3, R0, #3
ADD instruction, immediate mode
R3 <= R0 + x0003
R0 = x0000 = 0000 0000 0000 0000
#3 = x0003 = 0000 0000 0000 0011
(R0) ADD (#3) = x0003
Store the result back to R3
R0 x0000
R1 x0000
R2 x0002
R3 x0003
R4 x0000
R5 x0000
R0 x0000
R1 x0000
R2 x0002
R3 x0000
R4 x0000
R5 x0000
Solution 1
LEA R1, #9
PC (before fetch): x3003
PC (after fetch): x3004
DR = PC + SEXT(PCoffset9)
PC (after fetch) + SEXT(#9) = x3004 + x0009 = x300D
R1 = x300D
R0 x0000
R1 x300D
R2 x0002
R3 x0003
R4 x0000
R5 x0000
R0 x0000
R1 x0000
R2 x0002
R3 x0003
R4 x0000
R5 x0000
Solution 1
STR R3, R1, #3
Base + Offset Mode: STR SR, Base, offset6
mem[Base + SEXT(offset6)] = SR
SR = R3 = x0003
Base = R1 = x300D
Base + SEXT(offset6) = x300D + x0003 = x3010
Mem[x3010] = x0003
R0 x0000
R1 x300D
R2 x0002
R3 x0003
R4 x0000
R5 x0000
Memory address Content
x3010 x0003
x3011 ????
Memory address Content
x3010 ????
x3011 ????
Solution 1
STR R2, R1, #4
Base + Offset Mode: STR SR, Base, offset6
mem[Base + SEXT(offset6)] = SR
SR = R2 = x0002
Base = R1 = x300D
Base + SEXT(offset6) = x300D + x0004 = x3011
Mem[x3011] = x0002
R0 x0000
R1 x300D
R2 x0002
R3 x0003
R4 x0000
R5 x0000
Memory address Content
x3010 x0003
x3011 x0002
Memory address Content
x3010 x0003
x3011 ????
Solution 1
LDR R2, R1, #3
Base + Offset Mode: LDR DR, Base, offset6
DR = mem[Base + SEXT(offset6)]
Base = R1 = x300D
Base + SEXT(offset6) = x300D + x0003 = x3010
R2 = mem[x3010] = x0003
R0 x0000
R1 x300D
R2 x0003
R3 x0003
R4 x0000
R5 x0000
Memory address Content
x3010 x0003
x3011 x0002
R0 x0000
R1 x300D
R2 x0002
R3 x0003
R4 x0000
R5 x0000
Solution 1
LDR R3, R1, #4
Base + Offset Mode: LDR DR, Base, offset6
DR = mem[Base + SEXT(offset6)]
Base = R1 = x300D
Base + SEXT(offset6) = x300D + x0004 = x3011
R3 = mem[x3011] = x0002
Program end at here
Ans: Value of R1 is x300D
R0 x0000
R1 x300D
R2 x0003
R3 x0002
R4 x0000
R5 x0000
Memory address Content
x3010 x0003
x3011 x0002
R0 x0000
R1 x300D
R2 x0003
R3 x0003
R4 x0000
R5 x0000
Control Instructions
Conditional branch
BR(nzp) PCoffset9
Unconditional branch (Jump)
JMP Base
RET
Condition code register
There are 3 condition code registers in LC-3
N -- negative
Z -- zero
P -- positive
The condition code registers change when any following instructions are executed
ADD, AND, NOT, LD, LDR, LDI, LEA
ONLY one condition code register will be set in any time
Conditional branch - BR
Assembler format
BR(nzp) PCoffset9
Machine code format
Changing the program counter if the branch condition match
if ((n AND N) OR (z AND Z) OR (p AND P)) then
PC = PC(after fetch) + SEXT(PCoffset9)
Opcode n z p PCoffset9
[15:12] [11] [10] [9] [8:0]
0000 X X X XXXXXXXXX
n z p Branch when…
BR 0 0 0 NEVER branch
BRp 0 0 1 Condition code register P is set
BRz 0 1 0 Condition code register Z is set
BRzp 0 1 1 Condition code register Z OR P is set
BRn 1 0 0 Condition code register N is set
BRnp 1 0 1 Condition code register N OR P is set
BRnz 1 1 0 Condition code register N OR Z is set
BRnzp 1 1 1 ALWAYS branch
Unconditional branch - JMP
Assembler format
JMP BaseR
Machine code format
Set program counter to the content of base register
PC = BaseR
Opcode Redundancy Base Redundancy
[15:12] [11:9] [8:6] [5:0]
1100 000 XXX 000000
Unconditional branch - RET
Assembler format
RET
Machine code format
Set program counter to the content of R7
PC = R7
Opcode Redundancy
[15:12] [11:0]
1100 000111000000
Exercise 2
What should be the value of memory location x300A if the following program is executed?
Program:
.ORIG x3000
LEA R1, #8
AND R2, R2, #0 ; R2 is the count of the integers
ADD R2, R2, #2
LOOP ADD R4, R2, #0
STR R4, R1, #0
ADD R1, R1, #1
ADD R2, R2, #-1
BRp LOOP
EXIT TRAP 37 ; Program stop at here
.BLKW 12
Solution 2
LEA R1, #8
PC (before fetch): x3000
PC (after fetch): x3001
DR = PC + SEXT(PCoffset9)
PC (after fetch) + SEXT(#8) = x3001 + x0008 = x3009
R1 = x3009
R0 x0000
R1 x3009
R2 x0000
R3 x0000
R4 x0000
R5 x0000
N 0
Z 0
P 1
R0 x0000
R1 x0000
R2 x0000
R3 x0000
R4 x0000
R5 x0000
N ?
Z ?
P ?
Solution 2
AND R2, R2, #0
AND instruction, immediate mode
R2 <= (R2) AND (x0000)
Set R2 to x0000
Store the result back to R2
R0 x0000
R1 x3009
R2 x0000
R3 x0000
R4 x0000
R5 x0000
R0 x0000
R1 x3009
R2 x0000
R3 x0000
R4 x0000
R5 x0000
N 0
Z 1
P 0
N 0
Z 0
P 1
Solution 2
ADD R2, R2, #2
ADD instruction, immediate mode
R2 <= R2 + x0002
R2 = x0000 = 0000 0000 0000 0000
#2 = x0002 = 0000 0000 0000 0010
(R2) + (#2) = x0002
Store the result back to R2
R0 x0000
R1 x3009
R2 x0002
R3 x0000
R4 x0000
R5 x0000
N 0
Z 0
P 1
R0 x0000
R1 x3009
R2 x0000
R3 x0000
R4 x0000
R5 x0000
N 0
Z 1
P 0
Solution 2
LOOP ADD R4, R2, #0
LOOP is a label only
R4 <= R2 + x0000
R2 = x0002 = 0000 0000 0000 0010
#0 = x0000 = 0000 0000 0000 0000
(R2) + (#2) = x0002
Store the result back to R4
R0 x0000
R1 x3009
R2 x0002
R3 x0000
R4 x0002
R5 x0000
N 0
Z 0
P 1
R0 x0000
R1 x3009
R2 x0002
R3 x0000
R4 x0000
R5 x0000
Solution 2
STR R4, R1, #0
mem[Base + SEXT(offset6)] = SR
SR = R4 = x0002
Base = R1 = x3009
Base + SEXT(offset6) = x3009 + x0000 = x3009
Mem[x3009] = x0002
R0 x0000
R1 x3009
R2 x0002
R3 x0000
R4 x0002
R5 x0000
Memory address Content
x3009 x0002
x300A ????
N 0
Z 0
P 1
Memory address Content
x3009 ????
x300A ????
Solution 2
ADD R1, R1, #1
ADD instruction, immediate mode
R1 <= R1 + x0001
R1 = x3009 = 0011 0000 0000 1001
#1 = x0001 = 0000 0000 0000 0001
(R1) + (#1) = x300A
Store the result back to R1
R0 x0000
R1 x300A
R2 x0002
R3 x0000
R4 x0002
R5 x0000
Memory address Content
x3009 x0002
x300A ????
N 0
Z 0
P 1
R0 x0000
R1 x3009
R2 x0002
R3 x0000
R4 x0002
R5 x0000
Solution 2
ADD R2, R2, #-1
ADD instruction, immediate mode
R2 <= R2 + (-1)
R2 = x0002 = 0000 0000 0000 0010
#-1 = xFFFF = 1111 1111 1111 1111
(R2) + (#-1) = x0001
Store the result back to R2
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0002
R5 x0000
Memory address Content
x3009 x0002
x300A ????
N 0
Z 0
P 1
R0 x0000
R1 x300A
R2 x0002
R3 x0000
R4 x0002
R5 x0000
Solution 2
BRp LOOP
Branch when condition code register P is set
Since the condition code register P is 1
The PC will change to label LOOP
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0002
R5 x0000
Memory address Content
X3009 x0002
x300A ????
N 0
Z 0
P 1
Solution 2
LOOP ADD R4, R2, #0
R4 <= R2 + x0000
R2 = x0001 = 0000 0000 0000 0001
#0 = x0000 = 0000 0000 0000 0000
(R2) + (#0) = x0001
Store the result back to R4
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0001
R5 x0000
Memory address Content
x3009 x0002
x300A ????
N 0
Z 0
P 1
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0002
R5 x0000
Solution 2
STR R4, R1, #0
mem[Base + SEXT(offset6)] = SR
SR = R4 = x0001
Base = R1 = x300A
Base + SEXT(offset6) = x300A + x0000 = x300A
Mem[x300A] = x0001
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0001
R5 x0000
Memory address Content
x3009 x0002
x300A x0001
N 0
Z 0
P 1
Memory address Content
x3009 x0002
x300A ????
Solution 2
ADD R1, R1, #1
ADD instruction, immediate mode
R1 <= R1 + x0001
R1 = x300A = 0011 0000 0000 1010
#1 = x0001 = 0000 0000 0000 0001
(R1) + (#1) = x300B
Store the result back to R1
R0 x0000
R1 x300B
R2 x0001
R3 x0000
R4 x0001
R5 x0000
Memory address Content
x3009 x0002
x300A x0001
N 0
Z 0
P 1
R0 x0000
R1 x300A
R2 x0001
R3 x0000
R4 x0001
R5 x0000
Solution 2
ADD R2, R2, #-1
ADD instruction, immediate mode
R2 <= R2 + (-1)
R2 = x0001 = 0000 0000 0000 0001
#-1 = xFFFF = 1111 1111 1111 1111
(R2) + (#-1) = x0000
Store the result back to R2
R0 x0000
R1 x300B
R2 x0000
R3 x0000
R4 x0001
R5 x0000
Memory address Content
x3009 x0002
x300A x0001
N 0
Z 1
P 0
R0 x0000
R1 x300B
R2 x0001
R3 x0000
R4 x0001
R5 x0000
N 0
Z 0
P 1
Solution 2
BRp LOOP
Branch when condition code register P is set
Since the condition code register P is 0
Branch is not taken
PC = PC +1
Program end at here
Ans: Value of memory location x300A is x0001
R0 x0000
R1 x300B
R2 x0000
R3 x0000
R4 x0001
R5 x0000
Memory address Content
X3009 x0002
x300A x0001
N 0
Z 1
P 0
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